When a transaction has finished (including the PEC), the SMBus controller sets the INTR bit. Slightly optimize the polling loop by reading status before the first sleep.
Signed-off-by: Daniel Kurtz <[email protected]> --- drivers/i2c/busses/i2c-i801.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c index 51e11eb..8b74e1e 100644 --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c @@ -291,11 +291,11 @@ static void i801_wait_hwpec(struct i801_priv *priv) int timeout = 0; int status; - do { + status = inb_p(SMBHSTSTS(priv)); + while ((!(status & SMBHSTSTS_INTR)) && (timeout++ < MAX_RETRIES)) { usleep_range(250, 500); status = inb_p(SMBHSTSTS(priv)); - } while ((!(status & SMBHSTSTS_INTR)) - && (timeout++ < MAX_RETRIES)); + } if (timeout > MAX_RETRIES) dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n"); -- 1.7.7.3 -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
