Harini Katakam <harinik@...> writes:
>
> The I2C controller sends a NACK to the slave when transfer size register
> reaches zero, irrespective of the hold bit. So, in order to handle transfers
> greater than 252 bytes, the transfer size register has to be maintained at a
> value >= 1. This patch implements the same.
> The interrupt status is cleared at the beginning of the isr instead of
> the end, to avoid missing any interrupts - this is in sync with the new
> transfer handling.
>
> Signed-off-by: Harini Katakam <harinik@...>
> ---
>
> v2:
> No changes
>
Hi,
just had a look to the ISR code and found:
/* wait while fifo is full */
while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET)
(id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
this means, that (16 x 9 bit / SCL freq) is being waited in the ISR.
At 400 kHz SCL freq, this is 360 us. Is that a valid
workaround in respect to realtime behaviour?
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