>>>>> On 15 Feb 2005 03:43:10 -0500, Jes Sorensen <[EMAIL PROTECTED]> said:
>>>>> "Tony" == Luck, Tony <[EMAIL PROTECTED]> writes:
Tony> Is ia64 the only architecture that has uncached vs. cached
Tony> access issues? If so, the PG_arch_1 might have to be the
Tony> solution, but surely others have cache coherence problems too
Tony> if there are mixed cacheable and uncacheable access to the
Tony> same memory? In which case a new generic bit would be more
Tony> appropriate.
Jes> None of the ones I know well have this problem, but I have
Jes> little knowledge about this level of stuff on most
Jes> architectures. The ones that could have issues would probably
Jes> be like PPC, PARISC and maybe Alpha .....
Well, any CPU that allows overlapping mappings and does _any_ sort of
speculative accesses will have a problem. The only question is
whether you'll get an explicit error notification (e.g., MCA) or
silent data corruption.
--david
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