Alan Cox wrote:
Signed-off-by: Alan Cox <[EMAIL PROTECTED]>
Correct timing lists
Use DPLL when appropriate
Fix HPT372 UDMA 100 limit
Add HPT371N support
Reset the correct channel only not both when doing the pre_reset
processing
Pull DPLL clock from I/O not PCI space
Correct DPLL failure error handling
Looks OK to me, but... should I still apply this, given the recent
regression reports that hit LKML less than 48 hours ago?
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