Matt Sealey wrote:
Does anyone have any decent information on the purpose, performance
potential
or perhaps quirks of the "read prefetch" and "post write" buffer
features on
some IDE chipsets?
Oh, I've forgotten to reply about posting. :-)
There's a (little) wrtie post buffer in the IDE contoroller where it puts the
data from the PCI and GNTs the PCI transfer. The data later get output to the
IDE bus when the IDE timings are met, so the slow IDE transfers (which usually
need to wait for active/recovery time) doesn't hog the PCI too.
MBR, Sergei
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