Jeff Garzik wrote: > [...] > I'm starting to wonder if polling isn't just a dismal failure on SATA, > since the status register/etc. is all emulated. Thinking further along > those lines (how an ATA shadow register set is faked by the host > controller using FIS data), I wonder if polling -- per ATA spec -- > exposes a race between FIS reception and processing, and the update of > the ATA shadow register block.
Quite possibly - though the register set has been fake one way or another most of the time. This time it's a different fake, with two vendors getting to put the bits back together in a different order instead of one vendor's firmware team. The second generation controllers mostly seem to support/require using DMA to accomplish the operations named "PIO *" in the ATA/ATAPI spec. This will be a good thing(tm). I'm still trying to wrap my brain around what (if any) changes this will impose on libata - my hunch is that we will require a set of pio_xxx methods in ata_port_operations with suitable defaults that fall back to the tf_load/tf_read methods currently specified. Obviously, there will still be millions of first generation SATA controllers roaming the earth, and for stuff like SMART we need to make it play nicely with the other children. Damn. -- [EMAIL PROTECTED] Andy Warner Voice: (612) 801-8549 Fax: (208) 575-5634 - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
