On Wed, Feb 16, 2005 at 01:51:24PM -0700, Ajit Prem wrote: > > Thanks for the help. > > I printed the int_status register on interrupt > entry into vsc_sata_interrupt and got 0x8300. > According to the 31244 spec, this means (I have > only 1 disk connected to port 1) : > > -- SATA Port 1 IDE Interrupt (0x8000) > -- SATA Port 1 PHY Ready Interrupt (0x0200) > -- SATA Port 1 Phy Change State Interrupt (0x0100) > > Any patch I can try? > > Thanks, > > AP
Interesting that I haven't seen this, but then I only have the Vitesse part. Jeff, I don't see where libata-core writes to the SCR_ERROR register to clear the PHY Ready and Phy Change State interrupts. Is this something that sata_vsc is supposed to do in its interrupt handler? The core would miss such info if sata_vsc did this . . . . jeremy - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
