To save Jeff the trouble of replying.... > If NVidia followed the SATA-IO spec than should be possible to make them > work with NCQ, or do I think wrong of that? > Or isn't it possible?
The SATA spec defines the interface between the SATA controller and the hard drive. It does not define in any way the interface between the host processor and the SATA controller. There is no mention of controller registers and what the bits in them mean. Given that a good controller involves not only the registers themselves, but also a number of data structures pointed to by those registers, there's quite a bit of complexity there. Jeff has, quite sensibly, decided to focus his efforts on hardware whose manufacturers haven't made special effort to keep useful documentation away from him. (By declaring them "trade secrets" and threatening to punish any employees who might othrwise send him a copy.) > I found a Product Brief/Specification and a Blockdiagramm. That sort of thing is quite devoid of programming detail. It's like trying to navigate the New Jersey Turnpike using an early Dutch map of New Amsterdam. In fact, it was probably created before the programming interface was even designed. Somebody said "we want these features", drew up the spec, and handed that wishlist to the silicon hackers to fill in the details and implement. > Could it be possible to make reverse engeneering? Yes, but it's far more time-consuming. In particular, early silicon always has bugs, and finding the bugs and developing workarounds is a PITA when you have the specs; without them, it can be a nightmare. Jeff has plenty to do without making his life more difficult. Reverse-engineering NVIDIA is at the bottom of the list. He may never get to it in person. Of course, if you'd like to make an attempt... - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
