Jeff,
Patch 2/3: pdc2027x use "long" for counter data type
Description:
The pdc2027x byte counter value is only 30-bit, "long" should be big enough.
Changes:
- Change the counter data type from "unsigned long" to "long".
Patch tested OK on x86, power4 and power5 machines.
For your review, thanks.
Albert
Signed-off-by: Albert Lee <[EMAIL PROTECTED]>
--- 01_pdc_mmio/drivers/scsi/pata_pdc2027x.c 2005-08-11 16:43:25.000000000
+0800
+++ 02_pdc_long/drivers/scsi/pata_pdc2027x.c 2005-08-12 11:39:32.000000000
+0800
@@ -29,7 +29,7 @@
#include <asm/io.h>
#define DRV_NAME "pata_pdc2027x"
-#define DRV_VERSION "0.70"
+#define DRV_VERSION "0.71"
#undef PDC_DEBUG
#ifdef PDC_DEBUG
@@ -481,9 +481,9 @@
* @probe_ent: for the port address
*/
-static unsigned long pdc_read_counter(struct ata_probe_ent *probe_ent)
+static long pdc_read_counter(struct ata_probe_ent *probe_ent)
{
- unsigned long counter;
+ long counter;
int retry = 1;
u32 bccrl, bccrh, bccrlv, bccrhv;
@@ -612,7 +612,7 @@
static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent)
{
u32 scr;
- unsigned long start_count, end_count;
+ long start_count, end_count;
long pll_clock;
/* Read current counter value */
@@ -637,9 +637,9 @@
readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */
/* calculate the input clock in Hz */
- pll_clock = (long) ((start_count - end_count) * 10);
+ pll_clock = (start_count - end_count) * 10;
- PDPRINTK("start[%lu] end[%lu] \n", start_count, end_count);
+ PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
return pll_clock;
