> > The IRQ delivery is async to the I/O so this makes a lot of sense for all
> > cases.
>
> I don't think that's true unless the controller is doing something funky
> as in SET XFERMODE. Can you enlighten me?
It is true for all cases. There is no synchronization between interrupt
delivery and I/O cycles and both of them are asynchronous. It is
especially obvious on older APIC based boxes that use a 4 wire bus to
send interrupt messages around.
This leads to suprising sequences like
device raises IRQ
kernel blocks device IRQ at chip
kernel reads to post the block
kernel does other stuff
IRQ message finally arrives
IRQ taken
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