Nadav Har'El wrote:
When a single-CPU machine does a context switch, it doesn't do it in the
middle of a machine instruction, it does it afterwards.
This sentance is not universally true, though I don't have details of
contradicting examples on hand. Yes, astonishing as it may sound, some
CPUs save their internal state on interrupt, and resume mid-operation.
That is, unless my memory is playing tricks of me (which is not impossible).
But, like I mentioned, there might be hypothetical machines which don't have
any 32 bit (or 64 bit, or whatever) instructions, and when you write
double d=0.0;
in C, which actually gets done in machine language are two instructions which
separately set the two halfs of the data. In such a case, indeed a context
switch might happen between the two halfs. But, like I said, I don't know of
any modern CPU on which this happens for C's usual types (long, double, etc.).
Anyway, this problem - related to bus widths and cache-line lengths, is
indeed very real on SMP machines (though, if I remember correctly, they
aren't a problem on Pentium SMPs).
--
Shachar Shemesh
Lingnu Open Source Consulting ltd.
http://www.lingnu.com/
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