I am feeling sort of lost here. Just got a new laptop (Compaq Armada
M300) which according to docs, Windows driver and lspnp (output
attached) has some sort of SMC IrCC chip. Based on the Windows driver
installation files I've guessed that it is either a FDC37N971 or
FDC37N972, not yet supported by smc-ircc in the 2.2.18 kernel.
It looks like the IrCC part is identical to the FDC37N958FR so I
thought that adding the two FDC37N97x chips would just be a matter of
adding them to the detection code. Right. No matter what I do, I
cannot write or read from the config port at 0x370 or 0x3f0 at all. I
also tried booting DOS to run SMCs own findchip utility (which claims
support for FDC37N97x) and it couldn't find any SMC chip either.
One notable difference in the FDC37N97x chips is that the address of
the configuration register may be changed (part of the docs is quoted
below). I have started wondering if maybe Compaq does this. The BIOS
setup utility is a joke, and does not provide any useful information
or tunable options of interest at all. One question I cannot find any
answer to in the SMC manual is: If the BIOS changes the address of the
config register, then how does one locate the chip? Using CR26 and
CR27 is somewhat difficult without already knowing the address...
I am including my small diff for findchip. Doing the same change to the
driver should be easy if anyone has success finding a FDC37N97x with it.
Bj�rn
Quote from FDC37N972 docs:
CONFIGURATION REGISTERS BASE ADDRESS REGISTERS (VCC2)
The FDC37N972 configuration ports base address is relocatable beyond
the two addressing options provided by the MODE pin.
Registers CR26 and CR27 enable the relocatable configuration ports
base address function. CR26 is the configuration ports base address
least significant byte; CR27 is the most significant byte (TABLE
212).
The configuration ports base address is relocatable on even-byte
boundaries; i.e., A0 = 0 . Valid configuration ports base address
values are 0x0000 - 0x0FFE.
At power-up, the configuration ports base address is determined by
the MODE pin. To relocate the configuration ports base address after
power-up, first write the lower address byte (LSB) of the new base
address to CR26 and then write the upper address bits to CR27. NOTE:
writing CR27 changes the configuration ports base address.
The ability to relocate the configuration ports base address can
prevent address conflicts, particularly when tape drives are used.
--- irda-utils-0.9.13/findchip/smc.c.old Wed Nov 22 20:54:35 2000
+++ irda-utils-0.9.13/findchip/smc.c Thu Dec 28 21:55:26 2000
@@ -77,6 +77,8 @@
{ "FDC37C93xFR", {0x3f0, 0x370}, 0x55, 0x55, 0x20, 0x03, probe_58 },
{ "FDC37N957FR", {0x3f0, 0x370}, 0x55, 0x55, 0x20, 0x07, probe_58 },
{ "FDC37N958FR", {0x3f0, 0x370}, 0x55, 0x55, 0x20, 0x09, probe_58 },
+ { "FDC37N971", {0x3f0, 0x370}, 0x55, 0x55, 0x20, 0x0a, probe_58 },
+ { "FDC37N972", {0x3f0, 0x370}, 0x55, 0x55, 0x20, 0x0b, probe_58 },
{ 0 }
};
0e SMCf010 communications device: RS-232
flags: [dynamic]
allocated resources:
io 0x03e8-0x03ef [16-bit decode]
io 0x0100-0x0107 [16-bit decode]
irq 3 [high edge]
dma 5 [16 bit] [compat]
possible resources:
[start dep fn]
io 0x03e8-0x03ef [16-bit decode]
io base 0x0100-0x0130 align 0x10 len 0x08 [16-bit decode]
irq mask 0x06a8 [high edge]
dma 5 [16 bit] [compat]
[start dep fn]
io 0x02f8-0x02ff [16-bit decode]
io base 0x0100-0x0130 align 0x10 len 0x08 [16-bit decode]
irq mask 0x06a8 [high edge]
dma 5 [16 bit] [compat]
[start dep fn]
io 0x03f8-0x03ff [16-bit decode]
io base 0x0100-0x0130 align 0x10 len 0x08 [16-bit decode]
irq mask 0x06a8 [high edge]
dma 5 [16 bit] [compat]
[start dep fn]
io 0x02e8-0x02ef [16-bit decode]
io base 0x0100-0x0130 align 0x10 len 0x08 [16-bit decode]
irq mask 0x06a8 [high edge]
dma 5 [16 bit] [compat]
[start dep fn]
io 0x03e8-0x03ef [16-bit decode]
io base 0x0100-0x0130 align 0x10 len 0x08 [16-bit decode]
irq mask 0x06a8 [high edge]
dma mask 0x000c [8 bit] [compat]
[start dep fn]
io 0x02f8-0x02ff [16-bit decode]
io base 0x0100-0x0130 align 0x10 len 0x08 [16-bit decode]
irq mask 0x06a8 [high edge]
dma mask 0x000c [8 bit] [compat]
[start dep fn]
io 0x03f8-0x03ff [16-bit decode]
io base 0x0100-0x0130 align 0x10 len 0x08 [16-bit decode]
irq mask 0x06a8 [high edge]
dma mask 0x000c [8 bit] [compat]
[start dep fn]
io 0x02e8-0x02ef [16-bit decode]
io base 0x0100-0x0130 align 0x10 len 0x08 [16-bit decode]
irq mask 0x06a8 [high edge]
dma mask 0x000c [8 bit] [compat]
[end dep fn]
compatible devices:
PNP0511 Generic IRDA-compatible device
