Add a node for the OSM L3 on the Milos SoC and define the CPU OPP tables
to scale DDR & L3 bandwidths when CPU cores change frequency.
Tested with 7zip benchmark ("7z b") and membw [0] showing very close
results compared to disabling .sync_state and thus keeping all
interconnect bandwidths on maximum vote.
[0] https://github.com/doug65536/membw
Unfortunately there's no support upstream yet to have different
opp-peak-kBps values depending on whether the device is running on DDR4
or DDR5 RAM, which is where Milos should use different DDR votes. For
now the DDR5 values are used which are (usually) higher, but should
hopefully not cause any issues on devices with DDR4. TODO comments are
placed where they differ.
Signed-off-by: Luca Weiss <[email protected]>
---
Luca Weiss (4):
dt-bindings: interconnect: OSM L3: Document Milos OSM L3 compatible
arm64: dts: qcom: milos: add OSM L3 node
arm64: dts: qcom: milos: add CPU interconnect properties
arm64: dts: qcom: milos: add CPU OPP table with DDR & L3 bandwidths
.../bindings/interconnect/qcom,osm-l3.yaml | 1 +
arch/arm64/boot/dts/qcom/milos.dtsi | 344 +++++++++++++++++++++
2 files changed, 345 insertions(+)
---
base-commit: 1db6c7d7df786928c6fb52625f46f1f856158728
change-id: 20260710-milos-cpu-opp-26fb6c36be60
Best regards,
--
Luca Weiss <[email protected]>
