On Wed, Jul 15, 2026 at 03:06:55AM -0400, Esteban Urrutia via B4 Relay wrote: > From: Esteban Urrutia <[email protected]> > > Two versions of PLLs for v6 PHYs exist: v1 and v1.1. > These tables only cover v1.1 PLLs. > For serdes, the difference between v1 and v1.1 PLLs is the value written to > the BG_TIMER register. > This register is set to 0x0e for v1 PLLs and 0x0a for v1.1 PLLs. > As reference, SM8550 and SM8650 SoCs use v1.1 PLLs. > For RBR/HBR/HBR2/HBR3, most values change. > Make this distinction clear to avoid confusion when adding support for SoCs > making use of v1 PLLs.
Checking the hardware docs I see no mention of v1 or v1.1 for these PHYs. > > Signed-off-by: Esteban Urrutia <[email protected]> > --- > drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 90 > +++++++++++++++---------------- > 1 file changed, 45 insertions(+), 45 deletions(-) -- With best wishes Dmitry
