Hi Mark,
I will try my best to review this series, but I am new to this subject and
have just finished reading the Arm ARM chapter about this, so please be
patient with questions that may sound dumb or things that I got wrong.
On Wed, Aug 12, 2026 at 08:12:00PM +0100, Mark Brown wrote:
> The initial EL2 setup for GCS did not include disabling of EL1 usage of
> GCS instructions, also disable these traps.
>
> Fixes: ff5181d8a2a8 ("arm64/gcs: Provide basic EL2 setup to allow GCS usage
> at EL0 and EL1")
> Signed-off-by: Mark Brown <[email protected]>
> ---
> arch/arm64/include/asm/el2_setup.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/include/asm/el2_setup.h
> b/arch/arm64/include/asm/el2_setup.h
> index aa8ec9df8024..d308c6e6757d 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -393,6 +393,11 @@
> orr x0, x0, #HFGRTR_EL2_nGCS_EL1_MASK
> orr x0, x0, #HFGRTR_EL2_nGCS_EL0_MASK
>
> + /* Disable traps of GCS instructions at EL1 */
> + orr x2, x2, #HFGITR_EL2_nGCSEPP_MASK
> + orr x2, x2, #HFGITR_EL2_nGCSSTR_EL1_MASK
> + orr x2, x2, #HFGITR_EL2_nGCSPUSHM_EL1_MASK
> +
In the Arm ARM M.c, D24.2.70, we have that by setting the above bits we
will _not_ trap the following instructions to EL2:
- GCSPUSHX,
- GCSPOPCX,
- GCSPUSHM,
- GCSSTR,
- GCSSTTR (when PSTATE.UAO=1 or HCSR_EL2.{NV,NV1} = {1,1}.)
Which I understand to be the way of us saying that EL2 will not interfere
on nor manage those instructions that let software change the entries of
GCS. Is that correct?
As for the asm routine, x2 at this point have nBRBIALL and nBRBINJ already
set, and will be loaded to SYS_HFGITR_EL2 in the next block of
instructions.
Did I get it right? Is there any missing detail here?
Thanks!
Leo
