Sonic,
DDR RAM initialization values are highly SCLK specific - so if we allow to Re-program Clocks while Kernel boots. - Hard-coded init values are none sense - we need to provide proper values. -Michael ________________________________ From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of [EMAIL PROTECTED] Sent: Donnerstag, 29. November 2007 05:56 To: [email protected] Subject: [Linux-kernel-commits] [3953] trunk: Fix bug[#3726] Enable bf548 to Re-program Clocks while Kernel boots. Revision 3953 <http://blackfin.uclinux.org/gf/project/linux-kernel/scmsvn/?action=brow se&path=/&view=rev&root=linux-kernel&revision=3953> Author sonicz <http://blackfin.uclinux.org/gf/user/sonicz/> Date 2007-11-28 22:56:15 -0600 (Wed, 28 Nov 2007) Log Message Fix bug[#3726] <http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=Tra ckerItemEdit&tracker_item_id=3726> Enable bf548 to Re-program Clocks while Kernel boots. Reprogram DDR EBIU register properly for bf548. Diffstat arch/blackfin/mach-bf548/head.S | 47 ++++++++++++++++++++++++ include/asm-blackfin/mach-bf548/defBF54x_base.h | 4 ++ include/asm-blackfin/mach-bf548/mem_init.h | 4 ++ 3 files changed, 55 insertions(+) Modified Paths * trunk/arch/blackfin/mach-bf548/head.S * trunk/include/asm-blackfin/mach-bf548/defBF54x_base.h * trunk/include/asm-blackfin/mach-bf548/mem_init.h Diff Modified: trunk/arch/blackfin/mach-bf548/head.S (3952 => 3953) --- trunk/arch/blackfin/mach-bf548/head.S 2007-11-28 19:05:26 UTC (rev 3952) +++ trunk/arch/blackfin/mach-bf548/head.S 2007-11-29 04:56:15 UTC (rev 3953) @@ -324,12 +324,25 @@ w[p0] = r0.l; ssync; +#if defined(CONFIG_BF54x) + P2.H = hi(EBIU_RSTCTL); + P2.L = lo(EBIU_RSTCTL); + R0 = [P2]; + BITSET (R0, 3); +#else P2.H = hi(EBIU_SDGCTL); P2.L = lo(EBIU_SDGCTL); R0 = [P2]; BITSET (R0, 24); +#endif [P2] = R0; SSYNC; +#if defined(CONFIG_BF54x) +.LSRR_MODE: + R0 = [P2]; + CC = BITTST(R0, 4); + if !CC JUMP .LSRR_MODE; +#endif r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ r0 = r0 << 9; /* Shift it over, */ @@ -361,6 +374,39 @@ w[p0] = r0.l; ssync; +#if defined(CONFIG_BF54x) + P2.H = hi(EBIU_RSTCTL); + P2.L = lo(EBIU_RSTCTL); + R0 = [P2]; + CC = BITTST(R0, 0); + if CC jump .Lskipddrrst; + BITSET (R0, 0); +.Lskipddrrst: + BITCLR (R0, 3); + [P2] = R0; + SSYNC; + + p0.l = lo(EBIU_DDRCTL0); + p0.h = hi(EBIU_DDRCTL0); + r0.l = lo(mem_DDRCTL0); + r0.h = hi(mem_DDRCTL0); + [p0] = r0; + ssync; + + p0.l = lo(EBIU_DDRCTL1); + p0.h = hi(EBIU_DDRCTL1); + r0.l = lo(mem_DDRCTL1); + r0.h = hi(mem_DDRCTL1); + [p0] = r0; + ssync; + + p0.l = lo(EBIU_DDRCTL2); + p0.h = hi(EBIU_DDRCTL2); + r0.l = lo(mem_DDRCTL2); + r0.h = hi(mem_DDRCTL2); + [p0] = r0; + ssync; +#else p0.l = lo(EBIU_SDRRC); p0.h = hi(EBIU_SDRRC); r0 = mem_SDRRC; @@ -394,6 +440,7 @@ R1 = R1 | R0; [P2] = R1; SSYNC; +#endif p0.h = hi(SIC_IWR0); p0.l = lo(SIC_IWR0); Modified: trunk/include/asm-blackfin/mach-bf548/defBF54x_base.h (3952 => 3953) --- trunk/include/asm-blackfin/mach-bf548/defBF54x_base.h 2007-11-28 19:05:26 UTC (rev 3952) +++ trunk/include/asm-blackfin/mach-bf548/defBF54x_base.h 2007-11-29 04:56:15 UTC (rev 3953) @@ -2257,6 +2257,10 @@ #define CSEL 0x30 /* Core Select */ #define SSEL 0xf /* System Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ /* Bit masks for PLL_CTL */ Modified: trunk/include/asm-blackfin/mach-bf548/mem_init.h (3952 => 3953) --- trunk/include/asm-blackfin/mach-bf548/mem_init.h 2007-11-28 19:05:26 UTC (rev 3952) +++ trunk/include/asm-blackfin/mach-bf548/mem_init.h 2007-11-29 04:56:15 UTC (rev 3953) @@ -32,6 +32,10 @@ #if (CONFIG_MEM_MT46V32M16) #endif +#define mem_DDRCTL0 0x23FE8287 +#define mem_DDRCTL1 0x10022223 +#define mem_DDRCTL2 0x00000021 + #if defined CONFIG_CLKIN_HALF #define CLKIN_HALF 1 #else
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