Modified: trunk/drivers/ata/pata_bf54x.c (3967 => 3968)
--- trunk/drivers/ata/pata_bf54x.c 2007-11-30 14:26:21 UTC (rev 3967)
+++ trunk/drivers/ata/pata_bf54x.c 2007-11-30 14:39:14 UTC (rev 3968)
@@ -299,7 +299,7 @@
*/
n6 = num_clocks_min(t6min, fsclk);
if (mode >= 0 && mode <= 4 && n6 >= 1) {
- dev_info(adev->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
+ dev_dbg(adev->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
/* calculate the timing values for register transfers. */
while (mode > 0 && pio_fsclk[mode] > fsclk)
mode--;
@@ -376,7 +376,7 @@
mode = adev->dma_mode - XFER_UDMA_0;
if (mode >= 0 && mode <= 5) {
- dev_info(adev->ap->dev, "set udmamode: mode=%d\n", mode);
+ dev_dbg(adev->ap->dev, "set udmamode: mode=%d\n", mode);
/* the most restrictive timing value is t6 and tc,
* the DIOW - data hold. If one SCLK pulse is longer
* than this minimum value then register
@@ -433,7 +433,7 @@
mode = adev->dma_mode - XFER_MW_DMA_0;
if (mode >= 0 && mode <= 2) {
- dev_info(adev->ap->dev, "set mdmamode: mode=%d\n", mode);
+ dev_dbg(adev->ap->dev, "set mdmamode: mode=%d\n", mode);
/* the most restrictive timing value is tf, the DMACK to
* read data released. If one SCLK pulse is longer than
* this maximum value then the MDMA mode
@@ -697,7 +697,7 @@
write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal);
write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam);
write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah);
- dev_info(ap->dev, "hob: feat 0x%X nsect 0x%X, lba 0x%X "
+ dev_dbg(ap->dev, "hob: feat 0x%X nsect 0x%X, lba 0x%X "
"0x%X 0x%X\n",
tf->hob_feature,
tf->hob_nsect,
@@ -711,7 +711,7 @@
write_atapi_register(base, ATA_REG_LBAL, tf->lbal);
write_atapi_register(base, ATA_REG_LBAM, tf->lbam);
write_atapi_register(base, ATA_REG_LBAH, tf->lbah);
- dev_info(ap->dev, "feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
+ dev_dbg(ap->dev, "feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
tf->feature,
tf->nsect,
tf->lbal,
@@ -721,7 +721,7 @@
if (tf->flags & ATA_TFLAG_DEVICE) {
write_atapi_register(base, ATA_REG_DEVICE, tf->device);
- dev_info(ap->dev, "device 0x%X\n", tf->device);
+ dev_dbg(ap->dev, "device 0x%X\n", tf->device);
}
ata_wait_idle(ap);
@@ -782,7 +782,7 @@
const struct ata_taskfile *tf)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- dev_info(ap->dev, "ata%u: cmd 0x%X\n", ap->print_id, tf->command);
+ dev_dbg(ap->dev, "ata%u: cmd 0x%X\n", ap->print_id, tf->command);
write_atapi_register(base, ATA_REG_CMD, tf->command);
ata_pause(ap);
@@ -833,7 +833,7 @@
unsigned short config = WDSIZE_16;
struct scatterlist *sg;
- dev_info(qc->ap->dev, "in atapi dma setup\n");
+ dev_dbg(qc->ap->dev, "in atapi dma setup\n");
/* Program the ATA_CTRL register with dir */
if (qc->tf.flags & ATA_TFLAG_WRITE) {
/* fill the ATAPI DMA controller */
@@ -868,7 +868,7 @@
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
struct scatterlist *sg;
- dev_info(qc->ap->dev, "in atapi dma start\n");
+ dev_dbg(qc->ap->dev, "in atapi dma start\n");
if (!(ap->udma_mask || ap->mwdma_mask))
return;
@@ -886,7 +886,7 @@
sg_dma_address(sg) + sg_dma_len(sg));
}
enable_dma(CH_ATAPI_TX);
- dev_info(qc->ap->dev, "enable udma write\n");
+ dev_dbg(qc->ap->dev, "enable udma write\n");
/* Send ATA DMA write command */
bfin_exec_command(ap, &qc->tf);
@@ -896,7 +896,7 @@
| XFER_DIR));
} else {
enable_dma(CH_ATAPI_RX);
- dev_info(qc->ap->dev, "enable udma read\n");
+ dev_dbg(qc->ap->dev, "enable udma read\n");
/* Send ATA DMA read command */
bfin_exec_command(ap, &qc->tf);
@@ -933,7 +933,7 @@
struct ata_port *ap = qc->ap;
struct scatterlist *sg;
- dev_info(qc->ap->dev, "in atapi dma stop\n");
+ dev_dbg(qc->ap->dev, "in atapi dma stop\n");
if (!(ap->udma_mask || ap->mwdma_mask))
return;
@@ -1151,7 +1151,7 @@
host_stat |= ATA_DMA_ERR;
}
- dev_info(ap->dev, "ATAPI: host_stat=0x%x\n", host_stat);
+ dev_dbg(ap->dev, "ATAPI: host_stat=0x%x\n", host_stat);
return host_stat;
}
@@ -1207,7 +1207,7 @@
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- dev_info(ap->dev, "in atapi irq clear\n");
+ dev_dbg(ap->dev, "in atapi irq clear\n");
ATAPI_SET_INT_STATUS(base, 0x1FF);
}
@@ -1223,7 +1223,7 @@
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
u8 tmp;
- dev_info(ap->dev, "in atapi irq on\n");
+ dev_dbg(ap->dev, "in atapi irq on\n");
ap->ctl &= ~ATA_NIEN;
ap->last_ctl = ap->ctl;
@@ -1248,7 +1248,7 @@
unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY;
unsigned char status;
- dev_info(ap->dev, "in atapi irq ack\n");
+ dev_dbg(ap->dev, "in atapi irq ack\n");
status = ata_busy_wait(ap, bits, 1000);
if (status & bits)
if (ata_msg_err(ap))
@@ -1273,7 +1273,7 @@
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- dev_info(ap->dev, "in atapi dma freeze\n");
+ dev_dbg(ap->dev, "in atapi dma freeze\n");
ap->ctl |= ATA_NIEN;
ap->last_ctl = ap->ctl;
@@ -1345,7 +1345,7 @@
static void bfin_port_stop(struct ata_port *ap)
{
- dev_info(ap->dev, "in atapi port stop\n");
+ dev_dbg(ap->dev, "in atapi port stop\n");
if (ap->udma_mask != 0 || ap->mwdma_mask != 0) {
free_dma(CH_ATAPI_RX);
free_dma(CH_ATAPI_TX);
@@ -1354,7 +1354,7 @@
static int bfin_port_start(struct ata_port *ap)
{
- dev_info(ap->dev, "in atapi port start\n");
+ dev_dbg(ap->dev, "in atapi port start\n");
if (!(ap->udma_mask || ap->mwdma_mask))
return 0;
