Title: [3977] trunk: [!no_src_qa!]bug[#3726]
Configure DDR registers according to system clock.
- Revision
- 3977
- Author
- sonicz
- Date
- 2007-12-04 01:39:14 -0600 (Tue, 04 Dec 2007)
Log Message
[!no_src_qa!]bug[#3726] Configure DDR registers according to system clock.
Diffstat
arch/blackfin/Kconfig | 2 +
include/asm-blackfin/mach-bf548/defBF54x_base.h | 27 +++++++++++++-
include/asm-blackfin/mach-bf548/mem_init.h | 45 ++++++++++++++++++++++--
3 files changed, 69 insertions(+), 5 deletions(-)
Modified Paths
Diff
Modified: trunk/arch/blackfin/Kconfig (3976 => 3977)
--- trunk/arch/blackfin/Kconfig 2007-12-04 04:40:10 UTC (rev 3976)
+++ trunk/arch/blackfin/Kconfig 2007-12-04 07:39:14 UTC (rev 3977)
@@ -410,6 +410,7 @@
default 32 if BFIN533_EZKIT
default 64 if BFIN527_EZKIT
default 64 if BFIN537_STAMP
+ default 64 if BFIN548_EZKIT
default 64 if BFIN561_EZKIT
default 128 if BFIN533_STAMP
default 64 if PNAV10
@@ -417,6 +418,7 @@
config MEM_ADD_WIDTH
int "SDRAM Memory Address Width"
+ depends on (!BF54x)
default 9 if BFIN533_EZKIT
default 9 if BFIN561_EZKIT
default 9 if H8606_HVSISTEMAS
Modified: trunk/include/asm-blackfin/mach-bf548/defBF54x_base.h (3976 => 3977)
--- trunk/include/asm-blackfin/mach-bf548/defBF54x_base.h 2007-12-04 04:40:10 UTC (rev 3976)
+++ trunk/include/asm-blackfin/mach-bf548/defBF54x_base.h 2007-12-04 07:39:14 UTC (rev 3977)
@@ -1772,17 +1772,36 @@
#define TRP 0x3c0000 /* Pre charge-to-active command period */
#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
#define TRC 0x3c000000 /* Active-to-active time */
+#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
+#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
+#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
+#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
+#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
/* Bit masks for EBIU_DDRCTL1 */
#define TRCD 0xf /* Active-to-Read/write delay */
-#define MRD 0xf0 /* Mode register set to active */
+#define TMRD 0xf0 /* Mode register set to active */
#define TWR 0x300 /* Write Recovery time */
#define DDRDATWIDTH 0x3000 /* DDR data width */
#define EXTBANKS 0xc000 /* External banks */
#define DDRDEVWIDTH 0x30000 /* DDR device width */
#define DDRDEVSIZE 0xc0000 /* DDR device size */
-#define TWWTR 0xf0000000 /* Write-to-read delay */
+#define TWTR 0xf0000000 /* Write-to-read delay */
+#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
+#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
+#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
+#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
+#define DDR_DATWIDTH 0x2000 /* DDR data width */
+#define EXTBANK_1 0 /* 1 external bank */
+#define EXTBANK_2 0x4000 /* 2 external banks */
+#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
+#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
+#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
+#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
+#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
+#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
+#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
/* Bit masks for EBIU_DDRCTL2 */
@@ -1790,6 +1809,10 @@
#define CASLATENCY 0x70 /* CAS latency */
#define DLLRESET 0x100 /* DLL Reset */
#define REGE 0x1000 /* Register mode enable */
+#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
+#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
+#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
+#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
/* Bit masks for EBIU_DDRCTL3 */
Modified: trunk/include/asm-blackfin/mach-bf548/mem_init.h (3976 => 3977)
--- trunk/include/asm-blackfin/mach-bf548/mem_init.h 2007-12-04 04:40:10 UTC (rev 3976)
+++ trunk/include/asm-blackfin/mach-bf548/mem_init.h 2007-12-04 07:39:14 UTC (rev 3977)
@@ -28,14 +28,53 @@
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
+#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
#if (CONFIG_MEM_MT46V32M16_6T)
+#define DDR_SIZE DEVSZ_512
+#define DDR_WIDTH DEVWD_16
+
+#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
+#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
+#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
+#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
+#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
+
+#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
+#define DDR_tWTR DDR_TWTR(1)
+#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
+#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
#endif
-#define mem_DDRCTL0 0x23FE8287
-#define mem_DDRCTL1 0x10022223
-#define mem_DDRCTL2 0x00000021
+#if (CONFIG_MEM_GENERIC_BOARD)
+#define DDR_SIZE DEVSZ_512
+#define DDR_WIDTH DEVWD_16
+#define DDR_tRCD DDR_TRCD(3)
+#define DDR_tWTR DDR_TWTR(1)
+#define DDR_tWR DDR_TWR(2)
+#define DDR_tMRD DDR_TMRD(2)
+#define DDR_tRP DDR_TRP(3)
+#define DDR_tRAS DDR_TRAS(7)
+#define DDR_tRC DDR_TRC(10)
+#define DDR_tRFC DDR_TRFC(12)
+#define DDR_tREFI DDR_TREFI(1288)
+#endif
+
+#if (CONFIG_SCLK_HZ <= 133333333)
+#define DDR_CL CL_2
+#elif (CONFIG_SCLK_HZ <= 166666666)
+#define DDR_CL CL_2_5
+#else
+#define DDR_CL CL_3
+#endif
+
+#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
+#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
+ | DDR_tMRD | DDR_tWR | DDR_tRCD)
+#define mem_DDRCTL2 DDR_CL
+
+
#if defined CONFIG_CLKIN_HALF
#define CLKIN_HALF 1
#else
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