Title: [4041] trunk/arch/blackfin/mach-bf561/coreb.c: - Before DMA'
ing data to core B L1 memory, caches have to be flushed.
- Revision
- 4041
- Author
- vapier
- Date
- 2007-12-13 20:00:09 -0600 (Thu, 13 Dec 2007)
Log Message
- Before DMA'ing data to core B L1 memory, caches have to be flushed.
- Before DMA'ing data from core B L1 memory, caches have to be invalidated.
- Fix lock/unlock.
Signed-off-by: Enrik Berkhan <[EMAIL PROTECTED]>
Diffstat
coreb.c | 12 ++++++++----
1 files changed, 8 insertions(+), 4 deletions(-)
Modified Paths
Diff
Modified: trunk/arch/blackfin/mach-bf561/coreb.c (4040 => 4041)
--- trunk/arch/blackfin/mach-bf561/coreb.c 2007-12-13 19:20:47 UTC (rev 4040)
+++ trunk/arch/blackfin/mach-bf561/coreb.c 2007-12-14 02:00:09 UTC (rev 4041)
@@ -33,7 +33,9 @@
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/uaccess.h>
+#include <linux/fs.h>
#include <asm/dma.h>
+#include <asm/cacheflush.h>
#define MODULE_VER "v0.1"
@@ -90,11 +92,12 @@
coreb_dma_done = 0;
+ flush_dcache_range((unsigned long)buf, (unsigned long)(buf+len));
/* Source Channel */
set_dma_start_addr(CH_MEM_STREAM2_SRC, (unsigned long)buf);
set_dma_x_count(CH_MEM_STREAM2_SRC, len);
set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
- set_dma_config(CH_MEM_STREAM2_SRC, RESTART);
+ set_dma_config(CH_MEM_STREAM2_SRC, 0);
/* Destination Channel */
set_dma_start_addr(CH_MEM_STREAM2_DEST, coreb_base + p);
set_dma_x_count(CH_MEM_STREAM2_DEST, len);
@@ -135,11 +138,12 @@
coreb_dma_done = 0;
+ invalidate_dcache_range((unsigned long)buf, (unsigned long)(buf+len));
/* Source Channel */
set_dma_start_addr(CH_MEM_STREAM2_SRC, coreb_base + p);
set_dma_x_count(CH_MEM_STREAM2_SRC, len);
set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
- set_dma_config(CH_MEM_STREAM2_SRC, RESTART);
+ set_dma_config(CH_MEM_STREAM2_SRC, 0);
/* Destination Channel */
set_dma_start_addr(CH_MEM_STREAM2_DEST, (unsigned long)buf);
set_dma_x_count(CH_MEM_STREAM2_DEST, len);
@@ -266,7 +270,7 @@
coreb_status |= COREB_IS_RUNNING;
bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020);
SSYNC();
- spin_lock_irq(&coreb_lock);
+ spin_unlock_irq(&coreb_lock);
break;
#if defined(CONFIG_BF561_COREB_RESET)
case CMD_COREB_STOP:
@@ -275,7 +279,7 @@
bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020);
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
coreb_status &= ~COREB_IS_RUNNING;
- spin_lock_irq(&coreb_lock);
+ spin_unlock_irq(&coreb_lock);
break;
case CMD_COREB_RESET:
printk(KERN_INFO "Resetting Core B\n");
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