Title: [5313] trunk: Task[#4261] Make L2 SRAM cacheable.
- Revision
- 5313
- Author
- sonicz
- Date
- 2008-09-18 04:31:38 -0500 (Thu, 18 Sep 2008)
Log Message
Task[#4261] Make L2 SRAM cacheable.
Modified Paths
Diff
Modified: trunk/arch/blackfin/Kconfig (5312 => 5313)
--- trunk/arch/blackfin/Kconfig 2008-09-18 08:53:29 UTC (rev 5312)
+++ trunk/arch/blackfin/Kconfig 2008-09-18 09:31:38 UTC (rev 5313)
@@ -765,6 +765,13 @@
endchoice
+config BFIN_L2_CACHEABLE
+ bool "Cache L2 SRAM"
+ depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+ default n
+ help
+ Select to make L2 SRAM cacheable in L1 data and instruction cache.
+
config MPU
bool "Enable the memory protection unit (EXPERIMENTAL)"
default n
Modified: trunk/arch/blackfin/kernel/cplb-mpu/cplbinit.c (5312 => 5313)
--- trunk/arch/blackfin/kernel/cplb-mpu/cplbinit.c 2008-09-18 08:53:29 UTC (rev 5312)
+++ trunk/arch/blackfin/kernel/cplb-mpu/cplbinit.c 2008-09-18 09:31:38 UTC (rev 5313)
@@ -83,9 +83,19 @@
dcplb_tbl[i_d].addr = L1_DATA_A_START;
dcplb_tbl[i_d++].data = "" | PAGE_SIZE_4MB;
#endif
+#if L1_CODE_LENGTH > 0
icplb_tbl[i_i].addr = L1_CODE_START;
icplb_tbl[i_i++].data = "" | PAGE_SIZE_4MB;
+#endif
+ /* Cover L2 memory */
+#if L2_LENGTH > 0
+ dcplb_tbl[i_d].addr = L2_START;
+ dcplb_tbl[i_d++].data = "" | PAGE_SIZE_1MB;
+ icplb_tbl[i_i].addr = L2_START;
+ icplb_tbl[i_i++].data = "" | PAGE_SIZE_1MB;
+#endif
+
first_mask_dcplb = i_d;
first_switched_dcplb = i_d + (1 << page_mask_order);
first_switched_icplb = i_i;
Modified: trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c (5312 => 5313)
--- trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c 2008-09-18 08:53:29 UTC (rev 5312)
+++ trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c 2008-09-18 09:31:38 UTC (rev 5313)
@@ -168,8 +168,8 @@
.end = L2_START + L2_LENGTH,
.psize = SIZE_1M,
.attr = SWITCH_T | I_CPLB | D_CPLB,
- .i_conf = L2_MEMORY,
- .d_conf = L2_MEMORY,
+ .i_conf = L2_IMEMORY,
+ .d_conf = L2_DMEMORY,
.valid = (L2_LENGTH > 0),
.name = "L2 Memory",
},
Modified: trunk/include/asm-blackfin/cplb.h (5312 => 5313)
--- trunk/include/asm-blackfin/cplb.h 2008-09-18 08:53:29 UTC (rev 5312)
+++ trunk/include/asm-blackfin/cplb.h 2008-09-18 09:31:38 UTC (rev 5313)
@@ -55,7 +55,13 @@
#endif
#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
-#define L2_MEMORY (CPLB_COMMON)
+#ifdef CONFIG_BFIN_L2_CACHEABLE
+#define L2_IMEMORY (SDRAM_IGENERIC)
+#define L2_DMEMORY (SDRAM_DGENERIC)
+#else
+#define L2_IMEMORY (CPLB_COMMON)
+#define L2_DMEMORY (CPLB_COMMON)
+#endif
#define SDRAM_DNON_CHBL (CPLB_COMMON)
#define SDRAM_EBIU (CPLB_COMMON)
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
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