Title: [5853] trunk/arch/blackfin/mach-bf533/include/mach: Fix bug [#4708], irda build failed for BF533.
- Revision
- 5853
- Author
- gyang
- Date
- 2008-12-11 05:01:35 -0600 (Thu, 11 Dec 2008)
Log Message
Fix bug [#4708], irda build failed for BF533.
Modified Paths
Diff
Modified: trunk/arch/blackfin/mach-bf533/include/mach/blackfin.h (5852 => 5853)
--- trunk/arch/blackfin/mach-bf533/include/mach/blackfin.h 2008-12-11 02:38:43 UTC (rev 5852)
+++ trunk/arch/blackfin/mach-bf533/include/mach/blackfin.h 2008-12-11 11:01:35 UTC (rev 5853)
@@ -44,6 +44,13 @@
#define BFIN_UART_NR_PORTS 1
+#define CH_UART_RX CH_UART0_RX
+#define CH_UART_TX CH_UART0_TX
+
+#define IRQ_UART_ERROR IRQ_UART0_ERROR
+#define IRQ_UART_RX IRQ_UART0_RX
+#define IRQ_UART_TX IRQ_UART0_TX
+
#define OFFSET_THR 0x00 /* Transmit Holding register */
#define OFFSET_RBR 0x00 /* Receive Buffer register */
#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
Modified: trunk/arch/blackfin/mach-bf533/include/mach/dma.h (5852 => 5853)
--- trunk/arch/blackfin/mach-bf533/include/mach/dma.h 2008-12-11 02:38:43 UTC (rev 5852)
+++ trunk/arch/blackfin/mach-bf533/include/mach/dma.h 2008-12-11 11:01:35 UTC (rev 5853)
@@ -16,8 +16,8 @@
#define CH_SPORT1_RX 3
#define CH_SPORT1_TX 4
#define CH_SPI 5
-#define CH_UART_RX 6
-#define CH_UART_TX 7
+#define CH_UART0_RX 6
+#define CH_UART0_TX 7
#define CH_MEM_STREAM0_DEST 8 /* TX */
#define CH_MEM_STREAM0_SRC 9 /* RX */
#define CH_MEM_STREAM1_DEST 10 /* TX */
Modified: trunk/arch/blackfin/mach-bf533/include/mach/irq.h (5852 => 5853)
--- trunk/arch/blackfin/mach-bf533/include/mach/irq.h 2008-12-11 02:38:43 UTC (rev 5852)
+++ trunk/arch/blackfin/mach-bf533/include/mach/irq.h 2008-12-11 11:01:35 UTC (rev 5853)
@@ -90,16 +90,16 @@
#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
-#define IRQ_UART_ERROR 13 /*UART Error Interrupt */
+#define IRQ_UART0_ERROR 13 /*UART Error Interrupt */
#define IRQ_RTC 14 /*RTC Interrupt */
#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
-#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */
-#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */
+#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
+#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */
+#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */
#define IRQ_TMR0 23 /*Timer 0 */
#define IRQ_TMR1 24 /*Timer 1 */
#define IRQ_TMR2 25 /*Timer 2 */
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