Title: [5891] trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c: [#4729] add i/d cplb entries for the bootrom because there is functions/data in there we want to access
- Revision
- 5891
- Author
- vapier
- Date
- 2008-12-18 12:50:01 -0600 (Thu, 18 Dec 2008)
Log Message
[#4729] add i/d cplb entries for the bootrom because there is functions/data in there we want to access
Modified Paths
Diff
Modified: trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c (5890 => 5891)
--- trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c 2008-12-18 18:39:09 UTC (rev 5890)
+++ trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c 2008-12-18 18:50:01 UTC (rev 5891)
@@ -35,8 +35,8 @@
int first_switched_icplb PDT_ATTR;
int first_switched_dcplb PDT_ATTR;
-struct cplb_boundary dcplb_bounds[8] PDT_ATTR;
-struct cplb_boundary icplb_bounds[8] PDT_ATTR;
+struct cplb_boundary dcplb_bounds[10] PDT_ATTR;
+struct cplb_boundary icplb_bounds[10] PDT_ATTR;
int icplb_nr_bounds PDT_ATTR;
int dcplb_nr_bounds PDT_ATTR;
@@ -78,6 +78,9 @@
first_switched_dcplb = i_d;
first_switched_icplb = i_i;
+ BUG_ON(first_switched_dcplb > MAX_CPLBS);
+ BUG_ON(first_switched_icplb > MAX_CPLBS);
+
while (i_d < MAX_CPLBS)
d_tbl[i_d++].data = ""
while (i_i < MAX_CPLBS)
@@ -113,6 +116,12 @@
/* ASYNC banks. */
dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
dcplb_bounds[i_d++].data = ""
+ /* Addressing hole up to BootROM. */
+ dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
+ dcplb_bounds[i_d++].data = ""
+ /* BootROM -- largest one should be less than 1 meg. */
+ dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
+ dcplb_bounds[i_d++].data = ""
if (L2_LENGTH) {
/* Addressing hole up to L2 SRAM. */
dcplb_bounds[i_d].eaddr = L2_START;
@@ -144,6 +153,12 @@
icplb_bounds[i_i++].data = "" ?
SDRAM_IGENERIC : SDRAM_INON_CHBL);
}
+ /* Addressing hole up to BootROM. */
+ icplb_bounds[i_i].eaddr = BOOT_ROM_START;
+ icplb_bounds[i_i++].data = ""
+ /* BootROM -- largest one should be less than 1 meg. */
+ icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
+ icplb_bounds[i_i++].data = ""
if (L2_LENGTH) {
/* Addressing hole up to L2 SRAM, including the async bank. */
icplb_bounds[i_i].eaddr = L2_START;
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