Modified: trunk/drivers/char/bfin_ppi.c (6042 => 6043)
--- trunk/drivers/char/bfin_ppi.c 2009-01-30 12:52:40 UTC (rev 6042)
+++ trunk/drivers/char/bfin_ppi.c 2009-01-30 13:31:06 UTC (rev 6043)
@@ -57,6 +57,9 @@
#define PPI_DEVNAME "PPIdev"
#define PPI_MAJOR 252
+#define PPI_READ 0
+#define PPI_WRITE 1
+
const unsigned short per_req_ppi0_7[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_D0, P_PPI0_D1,\
P_PPI0_D2, P_PPI0_D3, P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, 0};
@@ -412,30 +415,6 @@
spin_lock_irqsave(&dev->lock, flags);
switch (cmd) {
- case CMD_PPI_PORT_ENABLE:
- {
- pr_debug("ppi_ioctl: CMD_PPI_PORT_ENABLE\n");
- regdata = dev->regs->ppi_control;
- if (arg)
- regdata |= PORT_EN;
- else
- regdata &= ~PORT_EN;
- conf->ppi_control = regdata;
- dev->regs->ppi_control = regdata;
- break;
- }
- case CMD_PPI_PORT_DIRECTION:
- {
- pr_debug("ppi_ioctl: CMD_PPI_PORT_DIRECTION\n");
- regdata = dev->regs->ppi_control;
- if (arg)
- regdata |= PORT_DIR;
- else
- regdata &= ~PORT_DIR;
- conf->ppi_control = regdata;
- dev->regs->ppi_control = regdata;
- break;
- }
case CMD_PPI_XFR_TYPE:
{
pr_debug("ppi_ioctl: CMD_PPI_XFR_TYPE\n");
@@ -497,6 +476,7 @@
#else
printk(KERN_ERR PPI_DEVNAME "ppi_ioctl: CMD_PPI_PACKING\
Not supported\n");
+ goto err_inval;
#endif
break;
}
@@ -563,9 +543,9 @@
conf->triggeredge = (unsigned short)arg;
regdata = dev->regs->ppi_control;
if (arg)
- regdata |= POLFS;
+ regdata |= POLS;
else
- regdata &= ~POLFS;
+ regdata &= ~POLS;
conf->ppi_control = regdata;
dev->regs->ppi_control = regdata;
break;
@@ -590,6 +570,7 @@
case CMD_PPI_SET_WRITECONTINUOUS:
{
printk(KERN_ERR PPI_DEVNAME "ppi_ioctl: CMD_PPI_SET_WRITECONTINUOUS Not supported\n");
+ goto err_inval;
break;
}
@@ -718,14 +699,6 @@
((unsigned long)buf) + count);
/*
- ** configure ppi port for DMA TIMOD RX (receive)
- ** Note: the rest of PPI control register bits should already be set
- ** with ioctls before read operation
- */
-
- dev->regs->ppi_control &= ~PORT_DIR;
-
- /*
** Configure DMA Controller
** WNR: memory write
** RESTART: flush DMA FIFO before beginning work unit
@@ -770,6 +743,7 @@
set_dma_x_modify(dma, stepSize);
/* configure PPI registers to match DMA registers */
+ dev->regs->ppi_control &= ~PORT_DIR;
dev->regs->ppi_count = conf->linelen - 1;
dev->regs->ppi_frame = conf->numlines;
dev->regs->ppi_delay = conf->delay;
@@ -901,10 +875,11 @@
set_dma_config(dma, conf->dma_config);
/* configure PPI registers to match DMA registers */
+
+ dev->regs->ppi_control |= PORT_DIR;
dev->regs->ppi_count = conf->linelen - 1;
dev->regs->ppi_frame = conf->numlines;
dev->regs->ppi_delay = conf->delay;
- SSYNC();
enable_dma(dma);
@@ -986,8 +961,6 @@
dev->conf.done = 1;
spin_unlock_irqrestore(&dev->lock, flags);
- ppi_reg_reset(dev);
-
/* Request DMA0 channel, and pass the interrupt handler */
if (peripheral_request_list(dev->per_ppi0_7, PPI_DEVNAME)) {
@@ -1008,6 +981,7 @@
return -EFAULT;
}
+ ppi_reg_reset(dev);
pr_debug("ppi_open: return\n");
return 0;
Modified: trunk/drivers/char/bfin_ppi.h (6042 => 6043)
--- trunk/drivers/char/bfin_ppi.h 2009-01-30 12:52:40 UTC (rev 6042)
+++ trunk/drivers/char/bfin_ppi.h 2009-01-30 13:31:06 UTC (rev 6043)
@@ -8,7 +8,7 @@
*
* Modified:
* Copyright (C) 2005 Eastman Kodak Company
- * Copyright 2005-2006 Analog Devices Inc.
+ * Copyright 2005-2009 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
@@ -32,15 +32,8 @@
#define __BFIN_PPI_H__
/*
-** FYI: Blackfin PPI register masks and offsets are defined in
-** mach-bfin533/defBF532.h
-*/
-
-/*
** ioctl commands
*/
-#define CMD_PPI_PORT_ENABLE 1
-#define CMD_PPI_PORT_DIRECTION 2
#define CMD_PPI_XFR_TYPE 3
#define CMD_PPI_PORT_CFG 4
#define CMD_PPI_FIELD_SELECT 5
@@ -60,19 +53,9 @@
#define CMD_PPI_GET_ALLCONFIG 32 /* For debug */
-#define PPI_IRQ_NUM 23
#define PPI_DMA_MAXSIZE (64*1024)
-#define PPI_READ 0
-#define PPI_WRITE 1
-
#define PPI_READ_DELAY 1
-#define CFG_PPI_PORT_ENABLE 1
-#define CFG_PPI_PORT_DISABLE 0
-
-#define CFG_PPI_PORT_DIR_RX 0
-#define CFG_PPI_PORT_DIR_TX 1
-
#define CFG_PPI_XFR_TYPE_646_AF 0
#define CFG_PPI_XFR_TYPE_646_EF 1
#define CFG_PPI_XFR_TYPE_646_VB 2
@@ -128,7 +111,4 @@
#define CFG_PPI_DIMS_1D 1
#define CFG_PPI_DIMS_2D 2
-#define POLFS 0x8000
-#define POLC 0x4000
-
#endif /* __BFIN_PPI_H__ */
