Title: [6533] branches/2009R1/arch/blackfin/mach-bf538/include/mach/portmux.h: [#5171] Requesting Peripherals failed for bfin spi during bf538 boot up
- Revision
- 6533
- Author
- hennerich
- Date
- 2009-06-02 05:43:20 -0500 (Tue, 02 Jun 2009)
Log Message
[#5171] Requesting Peripherals failed for bfin spi during bf538 boot up
Workaround bug [#5171]:
PORT C,D,E don?\226?\128?\153t fit struct gpio_port_t
PORT C,D,E are not GPIO interrupt capable
PORTxIO_FER (C,D,E) regs use inverted polarity (peripheral mode by
default)
Proper fix tracked in task: [#5193] BF548/9 PORT C,D,E GPIO support
Modified Paths
Diff
Modified: branches/2009R1/arch/blackfin/mach-bf538/include/mach/portmux.h (6532 => 6533)
--- branches/2009R1/arch/blackfin/mach-bf538/include/mach/portmux.h 2009-06-02 10:39:40 UTC (rev 6532)
+++ branches/2009R1/arch/blackfin/mach-bf538/include/mach/portmux.h 2009-06-02 10:43:20 UTC (rev 6533)
@@ -45,63 +45,63 @@
#define P_PPI0_D2 (P_DONTCARE)
#define P_PPI0_D3 (P_DONTCARE)
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1))
+#define P_CAN0_TX (P_DONTCARE | P_IDENT(GPIO_PC0))
+#define P_CAN0_RX (P_DONTCARE | P_IDENT(GPIO_PC1))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2))
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3))
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4))
-#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5))
-#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6))
-#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7))
-#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8))
-#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10))
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11))
-#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12))
-#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13))
+#define P_SPI1_MOSI (P_DONTCARE | P_IDENT(GPIO_PD0))
+#define P_SPI1_MISO (P_DONTCARE | P_IDENT(GPIO_PD1))
+#define P_SPI1_SCK (P_DONTCARE | P_IDENT(GPIO_PD2))
+#define P_SPI1_SS (P_DONTCARE | P_IDENT(GPIO_PD3))
+#define P_SPI1_SSEL1 (P_DONTCARE | P_IDENT(GPIO_PD4))
+#define P_SPI2_MOSI (P_DONTCARE | P_IDENT(GPIO_PD5))
+#define P_SPI2_MISO (P_DONTCARE | P_IDENT(GPIO_PD6))
+#define P_SPI2_SCK (P_DONTCARE | P_IDENT(GPIO_PD7))
+#define P_SPI2_SS (P_DONTCARE | P_IDENT(GPIO_PD8))
+#define P_SPI2_SSEL1 (P_DONTCARE | P_IDENT(GPIO_PD9))
+#define P_UART1_RX (P_DONTCARE | P_IDENT(GPIO_PD10))
+#define P_UART1_TX (P_DONTCARE | P_IDENT(GPIO_PD11))
+#define P_UART2_RX (P_DONTCARE | P_IDENT(GPIO_PD12))
+#define P_UART2_TX (P_DONTCARE | P_IDENT(GPIO_PD13))
-#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0))
-#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1))
-#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2))
-#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3))
-#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4))
-#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5))
-#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6))
-#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7))
-#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8))
-#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9))
-#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10))
-#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11))
-#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12))
-#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13))
-#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14))
-#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15))
+#define P_SPORT2_RSCLK (P_DONTCARE | P_IDENT(GPIO_PE0))
+#define P_SPORT2_RFS (P_DONTCARE | P_IDENT(GPIO_PE1))
+#define P_SPORT2_DRPRI (P_DONTCARE | P_IDENT(GPIO_PE2))
+#define P_SPORT2_DRSEC (P_DONTCARE | P_IDENT(GPIO_PE3))
+#define P_SPORT2_TSCLK (P_DONTCARE | P_IDENT(GPIO_PE4))
+#define P_SPORT2_TFS (P_DONTCARE | P_IDENT(GPIO_PE5))
+#define P_SPORT2_DTPRI (P_DONTCARE | P_IDENT(GPIO_PE6))
+#define P_SPORT2_DTSEC (P_DONTCARE | P_IDENT(GPIO_PE7))
+#define P_SPORT3_RSCLK (P_DONTCARE | P_IDENT(GPIO_PE8))
+#define P_SPORT3_RFS (P_DONTCARE | P_IDENT(GPIO_PE9))
+#define P_SPORT3_DRPRI (P_DONTCARE | P_IDENT(GPIO_PE10))
+#define P_SPORT3_DRSEC (P_DONTCARE | P_IDENT(GPIO_PE11))
+#define P_SPORT3_TSCLK (P_DONTCARE | P_IDENT(GPIO_PE12))
+#define P_SPORT3_TFS (P_DONTCARE | P_IDENT(GPIO_PE13))
+#define P_SPORT3_DTPRI (P_DONTCARE | P_IDENT(GPIO_PE14))
+#define P_SPORT3_DTSEC (P_DONTCARE | P_IDENT(GPIO_PE15))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
+#define P_PPI0_FS3 (P_DONTCARE | P_IDENT(GPIO_PF3))
+#define P_PPI0_D15 (P_DONTCARE | P_IDENT(GPIO_PF4))
+#define P_PPI0_D14 (P_DONTCARE | P_IDENT(GPIO_PF5))
+#define P_PPI0_D13 (P_DONTCARE | P_IDENT(GPIO_PF6))
+#define P_PPI0_D12 (P_DONTCARE | P_IDENT(GPIO_PF7))
+#define P_PPI0_D11 (P_DONTCARE | P_IDENT(GPIO_PF8))
+#define P_PPI0_D10 (P_DONTCARE | P_IDENT(GPIO_PF9))
+#define P_PPI0_D9 (P_DONTCARE | P_IDENT(GPIO_PF10))
+#define P_PPI0_D8 (P_DONTCARE | P_IDENT(GPIO_PF11))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
+#define P_PPI0_D4 (P_DONTCARE | P_IDENT(GPIO_PF15))
+#define P_PPI0_D5 (P_DONTCARE | P_IDENT(GPIO_PF14))
+#define P_PPI0_D6 (P_DONTCARE | P_IDENT(GPIO_PF13))
+#define P_PPI0_D7 (P_DONTCARE | P_IDENT(GPIO_PF12))
+#define P_SPI0_SSEL7 (P_DONTCARE | P_IDENT(GPIO_PF7))
+#define P_SPI0_SSEL6 (P_DONTCARE | P_IDENT(GPIO_PF6))
+#define P_SPI0_SSEL5 (P_DONTCARE | P_IDENT(GPIO_PF5))
+#define P_SPI0_SSEL4 (P_DONTCARE | P_IDENT(GPIO_PF4))
+#define P_SPI0_SSEL3 (P_DONTCARE | P_IDENT(GPIO_PF3))
+#define P_SPI0_SSEL2 (P_DONTCARE | P_IDENT(GPIO_PF2))
+#define P_SPI0_SSEL1 (P_DONTCARE | P_IDENT(GPIO_PF1))
+#define P_SPI0_SS (P_DONTCARE | P_IDENT(GPIO_PF0))
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
#endif /* _MACH_PORTMUX_H_ */
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