Title: [6806] branches/2009R1/arch/blackfin/include/asm/traps.h: update the exception message to r1.3 PRM.
- Revision
- 6806
- Author
- adamliyi
- Date
- 2009-06-19 03:49:13 -0500 (Fri, 19 Jun 2009)
Log Message
update the exception message to r1.3 PRM.
Modified Paths
Diff
Modified: branches/2009R1/arch/blackfin/include/asm/traps.h (6805 => 6806)
--- branches/2009R1/arch/blackfin/include/asm/traps.h 2009-06-19 07:51:44 UTC (rev 6805)
+++ branches/2009R1/arch/blackfin/include/asm/traps.h 2009-06-19 08:49:13 UTC (rev 6806)
@@ -111,9 +111,7 @@
level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
#define EXC_0x2A(level) \
"Instruction fetch misaligned address violation\n" \
- level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
- level " exception, the return address provided in RETX is the destination address which is\n" \
- level " misaligned, rather than the address of the offending instruction.\n"
+ level " - Attempted misaligned instruction cache fetch.\n"
#define EXC_0x2B(level) \
"CPLB protection violation\n" \
level " - Illegal instruction fetch access (memory protection violation).\n"
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