Title: [6815] trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c: fixup style a bit with the cache overhaul code
- Revision
- 6815
- Author
- vapier
- Date
- 2009-06-20 14:16:17 -0500 (Sat, 20 Jun 2009)
Log Message
fixup style a bit with the cache overhaul code
Modified Paths
Diff
Modified: trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c (6814 => 6815)
--- trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c 2009-06-20 15:00:29 UTC (rev 6814)
+++ trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c 2009-06-20 19:16:17 UTC (rev 6815)
@@ -153,9 +153,9 @@
#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
if (bfin_addr_dcacheable(addr)) {
d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-#ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
+# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
d_data |= CPLB_L1_AOW | CPLB_WT;
-#endif
+# endif
}
#endif
@@ -372,20 +372,17 @@
local_irq_save_hw(flags);
current_rwx_mask[cpu] = masks;
-#if L2_LENGTH != 0
- if (addr >= L2_START && addr < L2_START + L2_LENGTH) {
+ if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
addr = L2_START;
d_data = L2_DMEMORY;
- } else
-#endif
- {
- d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
+ } else {
+ d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- d_data |= CPLB_L1_CHBL;
-#ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_data |= CPLB_L1_AOW | CPLB_WT;
+ d_data |= CPLB_L1_CHBL;
+# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
+ d_data |= CPLB_L1_AOW | CPLB_WT;
+# endif
#endif
-#endif
}
disable_dcplb();
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