Title: [6899] branches/2009R1/arch/blackfin: backport pieces so access_ok() accepts Core B regions on non-SMP BF561 builds
- Revision
- 6899
- Author
- vapier
- Date
- 2009-07-01 10:04:29 -0500 (Wed, 01 Jul 2009)
Log Message
backport pieces so access_ok() accepts Core B regions on non-SMP BF561 builds
Modified Paths
Diff
Modified: branches/2009R1/arch/blackfin/kernel/process.c (6898 => 6899)
--- branches/2009R1/arch/blackfin/kernel/process.c 2009-07-01 15:02:04 UTC (rev 6898)
+++ branches/2009R1/arch/blackfin/kernel/process.c 2009-07-01 15:04:29 UTC (rev 6899)
@@ -372,6 +372,20 @@
&& addr + size <= L2_START + L2_LENGTH)
return 1;
#endif
+#if !defined(CONFIG_SMP) && defined(COREB_L1_CODE_START)
+ if (addr >= COREB_L1_CODE_START &&
+ addr + size <= COREB_L1_CODE_START + COREB_L1_CODE_LENGTH)
+ return 1;
+ if (addr >= COREB_L1_SCRATCH_START &&
+ addr + size <= COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH)
+ return 1;
+ if (addr >= COREB_L1_DATA_A_START &&
+ addr + size <= COREB_L1_DATA_A_START + COREB_L1_DATA_A_LENGTH)
+ return 1;
+ if (addr >= COREB_L1_DATA_B_START &&
+ addr + size <= COREB_L1_DATA_B_START + COREB_L1_DATA_B_LENGTH)
+ return 1;
+#endif
return 0;
}
EXPORT_SYMBOL(_access_ok);
Modified: branches/2009R1/arch/blackfin/mach-bf561/include/mach/mem_map.h (6898 => 6899)
--- branches/2009R1/arch/blackfin/mach-bf561/include/mach/mem_map.h 2009-07-01 15:02:04 UTC (rev 6898)
+++ branches/2009R1/arch/blackfin/mach-bf561/include/mach/mem_map.h 2009-07-01 15:04:29 UTC (rev 6899)
@@ -34,7 +34,6 @@
/* Memory Map for ADSP-BF561 processors */
-#ifdef CONFIG_BF561
#define COREA_L1_CODE_START 0xFFA00000
#define COREA_L1_DATA_A_START 0xFF800000
#define COREA_L1_DATA_B_START 0xFF900000
@@ -71,6 +70,28 @@
#define BFIN_DCACHESIZE (0*1024)
#define BFIN_DSUPBANKS 0
#endif /*CONFIG_BFIN_DCACHE*/
+
+/*
+ * If we are in SMP mode, then the cache settings of Core B will match
+ * the settings of Core A. If we aren't, then we assume Core B is not
+ * using any cache. This allows the rest of the kernel to work with
+ * the core in either mode as we are only loading user code into it and
+ * it is the user's problem to make sure they aren't doing something
+ * stupid there.
+ *
+ * Note that we treat the L1 code region as a contiguous blob to make
+ * the rest of the kernel simpler. Easier to check one region than a
+ * bunch of small ones. Again, possible misbehavior here is the fault
+ * of the user -- don't try to use memory that doesn't exist.
+ */
+#ifdef CONFIG_SMP
+# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH
+# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH
+# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH
+#else
+# define COREB_L1_CODE_LENGTH 0x14000
+# define COREB_L1_DATA_A_LENGTH 0x8000
+# define COREB_L1_DATA_B_LENGTH 0x8000
#endif
/* Level 2 Memory */
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