Diff
Modified: trunk/arch/blackfin/include/asm/cplb.h (7196 => 7197)
--- trunk/arch/blackfin/include/asm/cplb.h 2009-08-18 04:29:33 UTC (rev 7196)
+++ trunk/arch/blackfin/include/asm/cplb.h 2009-08-18 15:51:04 UTC (rev 7197)
@@ -126,48 +126,47 @@
#define FAULT_CPLBBITS 0x0000ffff
#ifndef __ASSEMBLY__
-static inline void disable_dcplb(void)
+
+static inline void _disable_cplb(u32 mmr, u32 mask)
{
- unsigned long ctrl;
- ctrl = bfin_read_DMEM_CONTROL();
- ctrl &= ~ENDCPLB;
+ u32 ctrl = bfin_read32(mmr) & ~mask;
/* CSYNC to ensure load store ordering */
- CSYNC();
- bfin_write_DMEM_CONTROL(ctrl);
- SSYNC();
+ __builtin_bfin_csync();
+ bfin_write32(mmr, ctrl);
+ __builtin_bfin_ssync();
}
-
-static inline void enable_dcplb(void)
+static inline void disable_cplb(u32 mmr, u32 mask)
{
- unsigned long ctrl;
- ctrl = bfin_read_DMEM_CONTROL();
- ctrl |= ENDCPLB;
- /* CSYNC to ensure load store ordering */
+ u32 ctrl = bfin_read32(mmr) & ~mask;
CSYNC();
- bfin_write_DMEM_CONTROL(ctrl);
+ bfin_write32(mmr, ctrl);
SSYNC();
}
+#define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB)
+#define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB)
+#define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB)
+#define disable_icplb() disable_cplb(IMEM_CONTROL, ENICPLB)
-static inline void disable_icplb(void)
+static inline void _enable_cplb(u32 mmr, u32 mask)
{
- unsigned long ctrl;
- ctrl = bfin_read_IMEM_CONTROL();
- ctrl &= ~ENICPLB;
+ u32 ctrl = bfin_read32(mmr) | mask;
/* CSYNC to ensure load store ordering */
- CSYNC();
- bfin_write_IMEM_CONTROL(ctrl);
- SSYNC();
+ __builtin_bfin_csync();
+ bfin_write32(mmr, ctrl);
+ __builtin_bfin_ssync();
}
-
-static inline void enable_icplb(void)
+static inline void enable_cplb(u32 mmr, u32 mask)
{
- unsigned long ctrl;
- ctrl = bfin_read_IMEM_CONTROL();
- ctrl |= ENICPLB;
- /* CSYNC to ensure load store ordering */
+ u32 ctrl = bfin_read32(mmr) | mask;
CSYNC();
- bfin_write_IMEM_CONTROL(ctrl);
+ bfin_write32(mmr, ctrl);
SSYNC();
}
+#define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB)
+#define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB)
+#define _enable_icplb() _enable_cplb(IMEM_CONTROL, ENICPLB)
+#define enable_icplb() enable_cplb(IMEM_CONTROL, ENICPLB)
+
#endif /* __ASSEMBLY__ */
+
#endif /* _CPLB_H */
Modified: trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c (7196 => 7197)
--- trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c 2009-08-18 04:29:33 UTC (rev 7196)
+++ trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c 2009-08-18 15:51:04 UTC (rev 7197)
@@ -159,10 +159,10 @@
dcplb_tbl[cpu][idx].addr = addr;
dcplb_tbl[cpu][idx].data = ""
- disable_dcplb();
+ _disable_dcplb();
bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
- enable_dcplb();
+ _enable_dcplb();
return 0;
}
@@ -249,10 +249,10 @@
icplb_tbl[cpu][idx].addr = addr;
icplb_tbl[cpu][idx].data = ""
- disable_icplb();
+ _disable_icplb();
bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
- enable_icplb();
+ _enable_icplb();
return 0;
}
@@ -301,19 +301,19 @@
nr_cplb_flush[cpu]++;
local_irq_save_hw(flags);
- disable_icplb();
+ _disable_icplb();
for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
icplb_tbl[cpu][i].data = ""
bfin_write32(ICPLB_DATA0 + i * 4, 0);
}
- enable_icplb();
+ _enable_icplb();
- disable_dcplb();
+ _disable_dcplb();
for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
dcplb_tbl[cpu][i].data = ""
bfin_write32(DCPLB_DATA0 + i * 4, 0);
}
- enable_dcplb();
+ _enable_dcplb();
local_irq_restore_hw(flags);
}
@@ -346,7 +346,7 @@
#endif
}
- disable_dcplb();
+ _disable_dcplb();
for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
dcplb_tbl[cpu][i].addr = addr;
dcplb_tbl[cpu][i].data = ""
@@ -354,6 +354,6 @@
bfin_write32(DCPLB_ADDR0 + i * 4, addr);
addr += PAGE_SIZE;
}
- enable_dcplb();
+ _enable_dcplb();
local_irq_restore_hw(flags);
}
Modified: trunk/arch/blackfin/kernel/cplb-nompu/cplbmgr.c (7196 => 7197)
--- trunk/arch/blackfin/kernel/cplb-nompu/cplbmgr.c 2009-08-18 04:29:33 UTC (rev 7196)
+++ trunk/arch/blackfin/kernel/cplb-nompu/cplbmgr.c 2009-08-18 15:51:04 UTC (rev 7197)
@@ -51,10 +51,10 @@
static inline void write_dcplb_data(int cpu, int idx, unsigned long data,
unsigned long addr)
{
- disable_dcplb();
+ _disable_dcplb();
bfin_write32(DCPLB_DATA0 + idx * 4, data);
bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
- enable_dcplb();
+ _enable_dcplb();
#ifdef CONFIG_CPLB_INFO
dcplb_tbl[cpu][idx].addr = addr;
@@ -65,10 +65,10 @@
static inline void write_icplb_data(int cpu, int idx, unsigned long data,
unsigned long addr)
{
- disable_icplb();
+ _disable_icplb();
bfin_write32(ICPLB_DATA0 + idx * 4, data);
bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
- enable_icplb();
+ _enable_icplb();
#ifdef CONFIG_CPLB_INFO
icplb_tbl[cpu][idx].addr = addr;
Modified: trunk/arch/blackfin/mach-common/pm.c (7196 => 7197)
--- trunk/arch/blackfin/mach-common/pm.c 2009-08-18 04:29:33 UTC (rev 7196)
+++ trunk/arch/blackfin/mach-common/pm.c 2009-08-18 15:51:04 UTC (rev 7197)
@@ -210,16 +210,16 @@
#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
flushinv_all_dcache();
#endif
- disable_dcplb();
- disable_icplb();
+ _disable_dcplb();
+ _disable_icplb();
bf53x_suspend_l1_mem(memptr);
do_hibernate(wakeup | vr_wakeup); /* Goodbye */
bf53x_resume_l1_mem(memptr);
- enable_icplb();
- enable_dcplb();
+ _enable_icplb();
+ _enable_dcplb();
bfin_gpio_pm_hibernate_restore();
blackfin_dma_resume();
