On Fri, 2009-09-11 at 12:43 -0400, Mike Frysinger wrote: > On Mon, Aug 24, 2009 at 22:29, <[email protected]> wrote: > > Log Message > > > > Fix typo > > > > Modified: trunk/arch/blackfin/mach-bf561/include/mach/mem_map.h (7231 => > > 7232) > > > > # define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH > > # define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH > > #else > > -# define COREB_L1_CODE_LENGTH 0x14000 > > +# define COREB_L1_CODE_LENGTH 0x8000 > > # define COREB_L1_DATA_A_LENGTH 0x8000 > > # define COREB_L1_DATA_B_LENGTH 0x8000 > > #endif > > this isnt a typo. you cant assume cache is enabled in core b which > means we have to grant access to it. thus we use a value that covers > L1 inst sram as well as L1 inst sram/cache, and a small hole of memory Thanks, you are right, I missed the small hole.
> that doesnt actually exists. it keeps code that does access checking > much simpler. in fact, the comment right above these defines explains > exactly why the values are what they are. > > what exactly was the problem that made you change this ? > -mike _______________________________________________ Linux-kernel-commits mailing list [email protected] https://blackfin.uclinux.org/mailman/listinfo/linux-kernel-commits
