Diff
Modified: trunk/arch/blackfin/include/asm/bitops.h (7394 => 7395)
--- trunk/arch/blackfin/include/asm/bitops.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/include/asm/bitops.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -81,8 +81,110 @@
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
-#include <asm-generic/bitops/non-atomic.h>
+/**
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ *p |= mask;
+}
+
+static inline void __clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+ *p &= ~mask;
+}
+
+/**
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to change
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __change_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+ *p ^= mask;
+}
+
+/**
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail. You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old = *p;
+
+ *p = old | mask;
+ return (old & mask) != 0;
+}
+
+/**
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail. You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old = *p;
+
+ *p = old & ~mask;
+ return (old & mask) != 0;
+}
+
+/* WARNING: non atomic and it can be reordered! */
+static inline int __test_and_change_bit(int nr,
+ volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old = *p;
+
+ *p = old ^ mask;
+ return (old & mask) != 0;
+}
+
+#ifndef CONFIG_SMP
+/**
+ * test_bit - Determine whether a bit is set
+ * @nr: bit number to test
+ * @addr: Address to start counting from
+ */
+static inline int test_bit(int nr, const volatile unsigned long *addr)
+{
+ return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
+}
+#endif
+
#include <asm-generic/bitops/find.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
Modified: trunk/arch/blackfin/include/asm/cache.h (7394 => 7395)
--- trunk/arch/blackfin/include/asm/cache.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/include/asm/cache.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -3,6 +3,7 @@
*/
#ifndef __ARCH_BLACKFIN_CACHE_H
#define __ARCH_BLACKFIN_CACHE_H
+#include <linux/linkage.h>
/*
* Bytes per L1 cache line
Added: trunk/arch/blackfin/include/asm/cdef_misc.h (0 => 7395)
--- trunk/arch/blackfin/include/asm/cdef_misc.h (rev 0)
+++ trunk/arch/blackfin/include/asm/cdef_misc.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -0,0 +1,192 @@
+/*
+ * File: arch/blackfin/include/asm/cdef_misc.h
+ * Based on: arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+ * Author:
+ *
+ * Created:
+ * Description: C SYSTEM MMR REGISTER READ/WRITE THAT NEED DISABLE INTERRUPT
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_MISC_H
+#define _CDEF_MISC_H
+
+#include <asm/irq.h>
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+ unsigned long flags = 0;
+#ifdef SIC_IWR0
+ unsigned long iwr0;
+#ifdef SIC_IWR1
+ unsigned long iwr1;
+#ifdef SIC_IWR2
+ unsigned long iwr2;
+#endif
+#endif
+#else
+ unsigned long iwr;
+#endif
+
+ if (val == bfin_read_PLL_CTL())
+ return;
+
+ local_irq_save_hw(flags);
+ /* Enable the PLL Wakeup bit in SIC IWR */
+#ifdef SIC_IWR0
+ iwr0 = bfin_read32(SIC_IWR0);
+#ifdef SIC_IWR1
+ iwr1 = bfin_read32(SIC_IWR1);
+#ifdef SIC_IWR2
+ iwr2 = bfin_read32(SIC_IWR2);
+ bfin_write32(SIC_IWR2, 0);
+#endif
+ bfin_write32(SIC_IWR1, 0);
+#endif
+ /* Only allow PPL Wakeup) */
+ bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+#else
+ iwr = bfin_read32(SIC_IWR);
+#endif
+
+ bfin_write16(PLL_CTL, val);
+ SSYNC();
+ asm("IDLE;");
+
+#ifdef SIC_IWR0
+ bfin_write32(SIC_IWR0, iwr0);
+#ifdef SIC_IWR1
+ bfin_write32(SIC_IWR1, iwr1);
+#ifdef SIC_IWR2
+ bfin_write32(SIC_IWR2, iwr2);
+#endif
+#endif
+#else
+ bfin_write32(SIC_IWR, iwr);
+#endif
+ local_irq_restore_hw(flags);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+ unsigned long flags = 0;
+#ifdef SIC_IWR0
+ unsigned long iwr0;
+#ifdef SIC_IWR1
+ unsigned long iwr1;
+#ifdef SIC_IWR2
+ unsigned long iwr2;
+#endif
+#endif
+#else
+ unsigned long iwr;
+#endif
+
+ if (val == bfin_read_VR_CTL())
+ return;
+
+ /* Enable the PLL Wakeup bit in SIC IWR */
+#ifdef SIC_IWR0
+ iwr0 = bfin_read32(SIC_IWR0);
+#ifdef SIC_IWR1
+ iwr1 = bfin_read32(SIC_IWR1);
+#ifdef SIC_IWR2
+ iwr2 = bfin_read32(SIC_IWR2);
+ bfin_write32(SIC_IWR2, 0);
+#endif
+ bfin_write32(SIC_IWR1, 0);
+#endif
+ /* Only allow PPL Wakeup) */
+ bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+#else
+ iwr = bfin_read32(SIC_IWR);
+ bfin_write32(SIC_IWR, IWR_ENABLE(0));
+#endif
+
+ bfin_write16(VR_CTL, val);
+ SSYNC();
+ asm("IDLE;");
+
+#ifdef SIC_IWR0
+ bfin_write32(SIC_IWR0, iwr0);
+#ifdef SIC_IWR1
+ bfin_write32(SIC_IWR1, iwr1);
+#ifdef SIC_IWR2
+ bfin_write32(SIC_IWR2, iwr2);
+#endif
+#endif
+#else
+ bfin_write32(SIC_IWR, iwr);
+#endif
+ local_irq_restore_hw(flags);
+}
+
+
+#ifdef BF533_FAMILY
+
+#if ANOMALY_05000311
+#define BFIN_WRITE_FIO_FLAG(name) \
+static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
+{ \
+ unsigned long flags; \
+ local_irq_save_hw(flags); \
+ bfin_write16(FIO_FLAG_##name, val); \
+ bfin_read_CHIPID(); \
+ local_irq_restore_hw(flags); \
+}
+BFIN_WRITE_FIO_FLAG(D)
+BFIN_WRITE_FIO_FLAG(C)
+BFIN_WRITE_FIO_FLAG(S)
+BFIN_WRITE_FIO_FLAG(T)
+
+#define BFIN_READ_FIO_FLAG(name) \
+static inline u16 bfin_read_FIO_FLAG_##name(void) \
+{ \
+ unsigned long flags; \
+ u16 ret; \
+ local_irq_save_hw(flags); \
+ ret = bfin_read16(FIO_FLAG_##name); \
+ bfin_read_CHIPID(); \
+ local_irq_restore_hw(flags); \
+ return ret; \
+}
+BFIN_READ_FIO_FLAG(D)
+BFIN_READ_FIO_FLAG(C)
+BFIN_READ_FIO_FLAG(S)
+BFIN_READ_FIO_FLAG(T)
+
+#else
+#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
+#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
+#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
+#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
+#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
+#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
+#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
+#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
+#endif
+
+#endif
+
+#endif
Property changes on: trunk/arch/blackfin/include/asm/cdef_misc.h
___________________________________________________________________
Added: svn:eol-style
Modified: trunk/arch/blackfin/include/asm/irqflags.h (7394 => 7395)
--- trunk/arch/blackfin/include/asm/irqflags.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/include/asm/irqflags.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -11,9 +11,6 @@
#ifdef CONFIG_SMP
# include <asm/pda.h>
# include <asm/processor.h>
-/* Forward decl needed due to cdef inter dependencies */
-static inline uint32_t __pure bfin_dspid(void);
-# define blackfin_core_id() (bfin_dspid() & 0xff)
# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
#else
extern unsigned long bfin_irq_flags;
Modified: trunk/arch/blackfin/include/asm/mem_map.h (7394 => 7395)
--- trunk/arch/blackfin/include/asm/mem_map.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/include/asm/mem_map.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -9,6 +9,7 @@
#define __BFIN_MEM_MAP_H__
#include <mach/mem_map.h>
+#include <mach/blackfin.h>
/* Every Blackfin so far has MMRs like this */
#ifndef COREMMR_BASE
@@ -36,15 +37,19 @@
# define L1_ROM_LENGTH 0
#endif
+
+#ifdef __ASSEMBLY__
/* Allow wonky SMP ports to override this */
-#ifndef GET_PDA_SAFE
-# define GET_PDA_SAFE(preg) \
+# ifndef GET_PDA_SAFE
+# define GET_PDA_SAFE(preg) \
preg.l = _cpu_pda; \
preg.h = _cpu_pda;
-# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
+# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
+# endif
-# ifndef __ASSEMBLY__
+#else /* ! __ASSEMBLY__ */
+# ifndef CONFIG_SMP
static inline unsigned long get_l1_scratch_start_cpu(int cpu)
{
return L1_SCRATCH_START;
@@ -77,8 +82,42 @@
{
return get_l1_data_b_start_cpu(0);
}
+# else
-# endif /* __ASSEMBLY__ */
-#endif /* !GET_PDA_SAFE */
+static inline unsigned long get_l1_scratch_start_cpu(int cpu)
+{
+ return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
+}
+static inline unsigned long get_l1_code_start_cpu(int cpu)
+{
+ return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
+}
+static inline unsigned long get_l1_data_a_start_cpu(int cpu)
+{
+ return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
+}
+static inline unsigned long get_l1_data_b_start_cpu(int cpu)
+{
+ return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
+}
+static inline unsigned long get_l1_scratch_start(void)
+{
+ return get_l1_scratch_start_cpu(bfin_read_CHIPID() & 0xff);
+}
+static inline unsigned long get_l1_code_start(void)
+{
+ return get_l1_code_start_cpu(bfin_read_CHIPID() & 0xff);
+}
+static inline unsigned long get_l1_data_a_start(void)
+{
+ return get_l1_data_a_start_cpu(bfin_read_CHIPID() & 0xff);
+}
+static inline unsigned long get_l1_data_b_start(void)
+{
+ return get_l1_data_b_start_cpu(bfin_read_CHIPID() & 0xff);
+}
+# endif
+#endif /* __ASSEMBLY__ */
+
#endif
Modified: trunk/arch/blackfin/include/asm/processor.h (7394 => 7395)
--- trunk/arch/blackfin/include/asm/processor.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/include/asm/processor.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -8,7 +8,7 @@
#define current_text_addr() ({ __label__ _l; _l: &&_l;})
#include <asm/ptrace.h>
-#include <asm/blackfin.h>
+#include <mach/blackfin.h>
static inline unsigned long rdusp(void)
{
@@ -128,6 +128,8 @@
return bfin_read_DSPID();
}
+#define blackfin_core_id() (bfin_dspid() & 0xff)
+
static inline uint32_t __pure bfin_compiled_revid(void)
{
#if defined(CONFIG_BF_REV_0_0)
Modified: trunk/arch/blackfin/include/asm/spinlock.h (7394 => 7395)
--- trunk/arch/blackfin/include/asm/spinlock.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/include/asm/spinlock.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -61,6 +61,8 @@
__raw_read_lock_asm(&rw->lock);
}
+#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
+
static inline int __raw_read_trylock(raw_rwlock_t *rw)
{
return __raw_read_trylock_asm(&rw->lock);
@@ -76,6 +78,8 @@
__raw_write_lock_asm(&rw->lock);
}
+#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
+
static inline int __raw_write_trylock(raw_rwlock_t *rw)
{
return __raw_write_trylock_asm(&rw->lock);
Modified: trunk/arch/blackfin/kernel/process.c (7394 => 7395)
--- trunk/arch/blackfin/kernel/process.c 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/kernel/process.c 2009-09-21 11:51:31 UTC (rev 7395)
@@ -172,7 +172,7 @@
regs->pc = new_ip;
if (current->mm)
regs->p5 = current->mm->start_data;
-#ifdef CONFIG_SMP
+#ifndef CONFIG_SMP
task_thread_info(current)->l1_task_info.stack_start =
(void *)current->mm->context.stack_start;
task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
Modified: trunk/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h (7394 => 7395)
--- trunk/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -31,8 +31,6 @@
#ifndef _CDEF_BF52X_H
#define _CDEF_BF52X_H
-#include <asm/blackfin.h>
-
#include "defBF51x_base.h"
/* Include core specific register pointer definitions */
@@ -1152,57 +1150,4 @@
#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
- unsigned long flags, iwr0, iwr1;
-
- if (val == bfin_read_PLL_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr0 = bfin_read32(SIC_IWR0);
- iwr1 = bfin_read32(SIC_IWR1);
- /* Only allow PPL Wakeup) */
- bfin_write32(SIC_IWR0, IWR_ENABLE(0));
- bfin_write32(SIC_IWR1, 0);
-
- bfin_write16(PLL_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SIC_IWR0, iwr0);
- bfin_write32(SIC_IWR1, iwr1);
- local_irq_restore_hw(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
- unsigned long flags, iwr0, iwr1;
-
- if (val == bfin_read_VR_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr0 = bfin_read32(SIC_IWR0);
- iwr1 = bfin_read32(SIC_IWR1);
- /* Only allow PPL Wakeup) */
- bfin_write32(SIC_IWR0, IWR_ENABLE(0));
- bfin_write32(SIC_IWR1, 0);
-
- bfin_write16(VR_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SIC_IWR0, iwr0);
- bfin_write32(SIC_IWR1, iwr1);
- local_irq_restore_hw(flags);
-}
-
#endif /* _CDEF_BF52X_H */
Modified: trunk/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h (7394 => 7395)
--- trunk/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -31,8 +31,6 @@
#ifndef _CDEF_BF52X_H
#define _CDEF_BF52X_H
-#include <asm/blackfin.h>
-
#include "defBF52x_base.h"
/* Include core specific register pointer definitions */
@@ -1152,57 +1150,4 @@
#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
- unsigned long flags, iwr0, iwr1;
-
- if (val == bfin_read_PLL_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr0 = bfin_read32(SIC_IWR0);
- iwr1 = bfin_read32(SIC_IWR1);
- /* Only allow PPL Wakeup) */
- bfin_write32(SIC_IWR0, IWR_ENABLE(0));
- bfin_write32(SIC_IWR1, 0);
-
- bfin_write16(PLL_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SIC_IWR0, iwr0);
- bfin_write32(SIC_IWR1, iwr1);
- local_irq_restore_hw(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
- unsigned long flags, iwr0, iwr1;
-
- if (val == bfin_read_VR_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr0 = bfin_read32(SIC_IWR0);
- iwr1 = bfin_read32(SIC_IWR1);
- /* Only allow PPL Wakeup) */
- bfin_write32(SIC_IWR0, IWR_ENABLE(0));
- bfin_write32(SIC_IWR1, 0);
-
- bfin_write16(VR_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SIC_IWR0, iwr0);
- bfin_write32(SIC_IWR1, iwr1);
- local_irq_restore_hw(flags);
-}
-
#endif /* _CDEF_BF52X_H */
Modified: trunk/arch/blackfin/mach-bf533/boards/stamp.c (7394 => 7395)
--- trunk/arch/blackfin/mach-bf533/boards/stamp.c 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/mach-bf533/boards/stamp.c 2009-09-21 11:51:31 UTC (rev 7395)
@@ -46,6 +46,7 @@
#include <asm/reboot.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>
+#include <asm/cdef_misc.h>
/*
* Name the Board for the /proc/cpuinfo
Modified: trunk/arch/blackfin/mach-bf533/include/mach/cdefBF532.h (7394 => 7395)
--- trunk/arch/blackfin/mach-bf533/include/mach/cdefBF532.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/mach-bf533/include/mach/cdefBF532.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -31,8 +31,6 @@
#ifndef _CDEF_BF532_H
#define _CDEF_BF532_H
-#include <asm/blackfin.h>
-
/*include all Core registers and bit definitions*/
#include "defBF532.h"
@@ -676,93 +674,4 @@
#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
-#if ANOMALY_05000311
-#define BFIN_WRITE_FIO_FLAG(name) \
-static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
-{ \
- unsigned long flags; \
- local_irq_save_hw(flags); \
- bfin_write16(FIO_FLAG_##name, val); \
- bfin_read_CHIPID(); \
- local_irq_restore_hw(flags); \
-}
-BFIN_WRITE_FIO_FLAG(D)
-BFIN_WRITE_FIO_FLAG(C)
-BFIN_WRITE_FIO_FLAG(S)
-BFIN_WRITE_FIO_FLAG(T)
-
-#define BFIN_READ_FIO_FLAG(name) \
-static inline u16 bfin_read_FIO_FLAG_##name(void) \
-{ \
- unsigned long flags; \
- u16 ret; \
- local_irq_save_hw(flags); \
- ret = bfin_read16(FIO_FLAG_##name); \
- bfin_read_CHIPID(); \
- local_irq_restore_hw(flags); \
- return ret; \
-}
-BFIN_READ_FIO_FLAG(D)
-BFIN_READ_FIO_FLAG(C)
-BFIN_READ_FIO_FLAG(S)
-BFIN_READ_FIO_FLAG(T)
-
-#else
-#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
-#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
-#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
-#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
-#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
-#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
-#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
-#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
-#endif
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
- unsigned long flags, iwr;
-
- if (val == bfin_read_PLL_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr = bfin_read32(SIC_IWR);
- /* Only allow PPL Wakeup) */
- bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
- bfin_write16(PLL_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SIC_IWR, iwr);
- local_irq_restore_hw(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
- unsigned long flags, iwr;
-
- if (val == bfin_read_VR_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr = bfin_read32(SIC_IWR);
- /* Only allow PPL Wakeup) */
- bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
- bfin_write16(VR_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SIC_IWR, iwr);
- local_irq_restore_hw(flags);
-}
-
#endif /* _CDEF_BF532_H */
Modified: trunk/arch/blackfin/mach-bf537/include/mach/cdefBF534.h (7394 => 7395)
--- trunk/arch/blackfin/mach-bf537/include/mach/cdefBF534.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/mach-bf537/include/mach/cdefBF534.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -32,8 +32,6 @@
#ifndef _CDEF_BF534_H
#define _CDEF_BF534_H
-#include <asm/blackfin.h>
-
/* Include all Core registers and bit definitions */
#include "defBF534.h"
@@ -1772,51 +1770,4 @@
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
- unsigned long flags, iwr;
-
- if (val == bfin_read_PLL_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr = bfin_read32(SIC_IWR);
- /* Only allow PPL Wakeup) */
- bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
- bfin_write16(PLL_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SIC_IWR, iwr);
- local_irq_restore_hw(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
- unsigned long flags, iwr;
-
- if (val == bfin_read_VR_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr = bfin_read32(SIC_IWR);
- /* Only allow PPL Wakeup) */
- bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
- bfin_write16(VR_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SIC_IWR, iwr);
- local_irq_restore_hw(flags);
-}
-
#endif /* _CDEF_BF534_H */
Modified: trunk/arch/blackfin/mach-bf538/include/mach/cdefBF538.h (7394 => 7395)
--- trunk/arch/blackfin/mach-bf538/include/mach/cdefBF538.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/mach-bf538/include/mach/cdefBF538.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -31,8 +31,6 @@
#ifndef _CDEF_BF538_H
#define _CDEF_BF538_H
-#include <asm/blackfin.h>
-
/*include all Core registers and bit definitions*/
#include "defBF539.h"
@@ -2112,57 +2110,4 @@
#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
- unsigned long flags, iwr0, iwr1;
-
- if (val == bfin_read_PLL_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr0 = bfin_read32(SIC_IWR0);
- iwr1 = bfin_read32(SIC_IWR1);
- /* Only allow PPL Wakeup) */
- bfin_write32(SIC_IWR0, IWR_ENABLE(0));
- bfin_write32(SIC_IWR1, 0);
-
- bfin_write16(PLL_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SIC_IWR0, iwr0);
- bfin_write32(SIC_IWR1, iwr1);
- local_irq_restore_hw(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
- unsigned long flags, iwr0, iwr1;
-
- if (val == bfin_read_VR_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr0 = bfin_read32(SIC_IWR0);
- iwr1 = bfin_read32(SIC_IWR1);
- /* Only allow PPL Wakeup) */
- bfin_write32(SIC_IWR0, IWR_ENABLE(0));
- bfin_write32(SIC_IWR1, 0);
-
- bfin_write16(VR_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SIC_IWR0, iwr0);
- bfin_write32(SIC_IWR1, iwr1);
- local_irq_restore_hw(flags);
-}
-
#endif
Modified: trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h (7394 => 7395)
--- trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -31,8 +31,6 @@
#ifndef _CDEF_BF54X_H
#define _CDEF_BF54X_H
-#include <asm/blackfin.h>
-
#include "defBF54x_base.h"
/* ************************************************************** */
@@ -2691,64 +2689,5 @@
#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST
#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
- unsigned long flags, iwr0, iwr1, iwr2;
-
- if (val == bfin_read_PLL_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr0 = bfin_read32(SIC_IWR0);
- iwr1 = bfin_read32(SIC_IWR1);
- iwr2 = bfin_read32(SIC_IWR2);
- /* Only allow PPL Wakeup) */
- bfin_write32(SIC_IWR0, IWR_ENABLE(0));
- bfin_write32(SIC_IWR1, 0);
- bfin_write32(SIC_IWR2, 0);
-
- bfin_write16(PLL_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SIC_IWR0, iwr0);
- bfin_write32(SIC_IWR1, iwr1);
- bfin_write32(SIC_IWR2, iwr2);
- local_irq_restore_hw(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
- unsigned long flags, iwr0, iwr1, iwr2;
-
- if (val == bfin_read_VR_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr0 = bfin_read32(SIC_IWR0);
- iwr1 = bfin_read32(SIC_IWR1);
- iwr2 = bfin_read32(SIC_IWR2);
- /* Only allow PPL Wakeup) */
- bfin_write32(SIC_IWR0, IWR_ENABLE(0));
- bfin_write32(SIC_IWR1, 0);
- bfin_write32(SIC_IWR2, 0);
-
- bfin_write16(VR_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SIC_IWR0, iwr0);
- bfin_write32(SIC_IWR1, iwr1);
- bfin_write32(SIC_IWR2, iwr2);
- local_irq_restore_hw(flags);
-}
-
#endif /* _CDEF_BF54X_H */
Modified: trunk/arch/blackfin/mach-bf561/include/mach/cdefBF561.h (7394 => 7395)
--- trunk/arch/blackfin/mach-bf561/include/mach/cdefBF561.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/mach-bf561/include/mach/cdefBF561.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -31,8 +31,6 @@
#ifndef _CDEF_BF561_H
#define _CDEF_BF561_H
-#include <asm/blackfin.h>
-
/* include all Core registers and bit definitions */
#include "defBF561.h"
@@ -1555,57 +1553,4 @@
#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA1_D1_START_ADDR()
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA1_D1_START_ADDR(val)
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
- unsigned long flags, iwr0, iwr1;
-
- if (val == bfin_read_PLL_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr0 = bfin_read32(SICA_IWR0);
- iwr1 = bfin_read32(SICA_IWR1);
- /* Only allow PPL Wakeup) */
- bfin_write32(SICA_IWR0, IWR_ENABLE(0));
- bfin_write32(SICA_IWR1, 0);
-
- bfin_write16(PLL_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SICA_IWR0, iwr0);
- bfin_write32(SICA_IWR1, iwr1);
- local_irq_restore_hw(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
- unsigned long flags, iwr0, iwr1;
-
- if (val == bfin_read_VR_CTL())
- return;
-
- local_irq_save_hw(flags);
- /* Enable the PLL Wakeup bit in SIC IWR */
- iwr0 = bfin_read32(SICA_IWR0);
- iwr1 = bfin_read32(SICA_IWR1);
- /* Only allow PPL Wakeup) */
- bfin_write32(SICA_IWR0, IWR_ENABLE(0));
- bfin_write32(SICA_IWR1, 0);
-
- bfin_write16(VR_CTL, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_write32(SICA_IWR0, iwr0);
- bfin_write32(SICA_IWR1, iwr1);
- local_irq_restore_hw(flags);
-}
-
#endif /* _CDEF_BF561_H */
Modified: trunk/arch/blackfin/mach-bf561/include/mach/mem_map.h (7394 => 7395)
--- trunk/arch/blackfin/mach-bf561/include/mach/mem_map.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/mach-bf561/include/mach/mem_map.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -175,43 +175,7 @@
dreg = [preg]; \
dreg = ROT dreg BY -1; \
dreg = CC;
-
-static inline unsigned long get_l1_scratch_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
-}
-static inline unsigned long get_l1_code_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
-}
-static inline unsigned long get_l1_data_a_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
-}
-static inline unsigned long get_l1_data_b_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
-}
-
-static inline unsigned long get_l1_scratch_start(void)
-{
- return get_l1_scratch_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_code_start(void)
-{
- return get_l1_code_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_data_a_start(void)
-{
- return get_l1_data_a_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_data_b_start(void)
-{
- return get_l1_data_b_start_cpu(blackfin_core_id());
-}
-
#endif /* CONFIG_SMP */
-
#endif /* __ASSEMBLY__ */
#endif
Modified: trunk/arch/blackfin/mach-bf561/include/mach/smp.h (7394 => 7395)
--- trunk/arch/blackfin/mach-bf561/include/mach/smp.h 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/mach-bf561/include/mach/smp.h 2009-09-21 11:51:31 UTC (rev 7395)
@@ -11,8 +11,6 @@
void platform_secondary_init(unsigned int cpu);
-void platform_request_ipi(int (*handler)(int, void *));
-
void platform_send_ipi(cpumask_t callmap);
void platform_send_ipi_cpu(unsigned int cpu);
Modified: trunk/arch/blackfin/mach-common/dpmc.c (7394 => 7395)
--- trunk/arch/blackfin/mach-common/dpmc.c 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/mach-common/dpmc.c 2009-09-21 11:51:31 UTC (rev 7395)
@@ -16,6 +16,7 @@
#include <asm/delay.h>
#include <asm/dpmc.h>
+#include <asm/cdef_misc.h>
#define DRIVER_NAME "bfin dpmc"
Modified: trunk/arch/blackfin/mach-common/smp.c (7394 => 7395)
--- trunk/arch/blackfin/mach-common/smp.c 2009-09-21 10:59:01 UTC (rev 7394)
+++ trunk/arch/blackfin/mach-common/smp.c 2009-09-21 11:51:31 UTC (rev 7395)
@@ -33,6 +33,7 @@
#include <linux/mm.h>
#include <linux/cpu.h>
#include <linux/smp.h>
+#include <linux/cpumask.h>
#include <linux/seq_file.h>
#include <linux/irq.h>
#include <asm/atomic.h>
@@ -56,12 +57,8 @@
*init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
*init_saved_dcplb_fault_addr_coreb;
-cpumask_t cpu_possible_map;
-EXPORT_SYMBOL(cpu_possible_map);
+void __init platform_request_ipi(irq_handler_t handler);
-cpumask_t cpu_online_map;
-EXPORT_SYMBOL(cpu_online_map);
-
#define BFIN_IPI_RESCHEDULE 0
#define BFIN_IPI_CALL_FUNC 1
#define BFIN_IPI_CPU_STOP 2
@@ -449,7 +446,7 @@
{
platform_prepare_cpus(max_cpus);
ipi_queue_init();
- platform_request_ipi(&ipi_handler);
+ platform_request_ipi(ipi_handler);
}
void __init smp_cpus_done(unsigned int max_cpus)
