Diff
Modified: trunk/arch/blackfin/mach-bf518/include/mach/anomaly.h (7743 => 7744)
--- trunk/arch/blackfin/mach-bf518/include/mach/anomaly.h 2009-11-02 11:33:21 UTC (rev 7743)
+++ trunk/arch/blackfin/mach-bf518/include/mach/anomaly.h 2009-11-03 02:27:25 UTC (rev 7744)
@@ -74,6 +74,10 @@
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
@@ -138,5 +142,6 @@
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000475 (0)
#endif
Modified: trunk/arch/blackfin/mach-bf527/include/mach/anomaly.h (7743 => 7744)
--- trunk/arch/blackfin/mach-bf527/include/mach/anomaly.h 2009-11-02 11:33:21 UTC (rev 7743)
+++ trunk/arch/blackfin/mach-bf527/include/mach/anomaly.h 2009-11-03 02:27:25 UTC (rev 7744)
@@ -204,6 +204,10 @@
#define ANOMALY_05000467 (1)
/* PLL Latches Incorrect Settings During Reset */
#define ANOMALY_05000469 (1)
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
@@ -255,5 +259,6 @@
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000475 (0)
#endif
Modified: trunk/arch/blackfin/mach-bf533/include/mach/anomaly.h (7743 => 7744)
--- trunk/arch/blackfin/mach-bf533/include/mach/anomaly.h 2009-11-02 11:33:21 UTC (rev 7743)
+++ trunk/arch/blackfin/mach-bf533/include/mach/anomaly.h 2009-11-03 02:27:25 UTC (rev 7744)
@@ -206,6 +206,10 @@
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible.
@@ -354,5 +358,6 @@
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000475 (0)
#endif
Modified: trunk/arch/blackfin/mach-bf537/include/mach/anomaly.h (7743 => 7744)
--- trunk/arch/blackfin/mach-bf537/include/mach/anomaly.h 2009-11-02 11:33:21 UTC (rev 7743)
+++ trunk/arch/blackfin/mach-bf537/include/mach/anomaly.h 2009-11-03 02:27:25 UTC (rev 7744)
@@ -160,6 +160,10 @@
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
@@ -207,5 +211,6 @@
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000475 (0)
#endif
Modified: trunk/arch/blackfin/mach-bf538/include/mach/anomaly.h (7743 => 7744)
--- trunk/arch/blackfin/mach-bf538/include/mach/anomaly.h 2009-11-02 11:33:21 UTC (rev 7743)
+++ trunk/arch/blackfin/mach-bf538/include/mach/anomaly.h 2009-11-03 02:27:25 UTC (rev 7744)
@@ -132,6 +132,10 @@
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
@@ -181,5 +185,6 @@
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000475 (0)
#endif
Modified: trunk/arch/blackfin/mach-bf548/include/mach/anomaly.h (7743 => 7744)
--- trunk/arch/blackfin/mach-bf548/include/mach/anomaly.h 2009-11-02 11:33:21 UTC (rev 7743)
+++ trunk/arch/blackfin/mach-bf548/include/mach/anomaly.h 2009-11-03 02:27:25 UTC (rev 7744)
@@ -28,6 +28,8 @@
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
+/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
+#define ANOMALY_05000220 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
@@ -204,8 +206,14 @@
#define ANOMALY_05000466 (1)
/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
#define ANOMALY_05000467 (1)
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
#define ANOMALY_05000474 (1)
+/* Core Hang With L2/L3 Configured in Writeback Cache Mode */
+#define ANOMALY_05000475 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
@@ -221,7 +229,6 @@
#define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
-#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
Modified: trunk/arch/blackfin/mach-bf561/include/mach/anomaly.h (7743 => 7744)
--- trunk/arch/blackfin/mach-bf561/include/mach/anomaly.h 2009-11-02 11:33:21 UTC (rev 7743)
+++ trunk/arch/blackfin/mach-bf561/include/mach/anomaly.h 2009-11-03 02:27:25 UTC (rev 7744)
@@ -288,6 +288,12 @@
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* Core Hang With L2/L3 Configured in Writeback Cache Mode */
+#define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000119 (0)
