Title: [7872] trunk/arch/blackfin/include/asm/bfin_sport.h: bfin_sport: improve mmr struct layout and allow people to access the tx/rx regs as either 16 or 32 bits, and include a helper for working around anomaly 473
- Revision
- 7872
- Author
- vapier
- Date
- 2009-11-25 01:48:10 -0500 (Wed, 25 Nov 2009)
Log Message
bfin_sport: improve mmr struct layout and allow people to access the tx/rx regs as either 16 or 32 bits, and include a helper for working around anomaly 473
Modified Paths
Diff
Modified: trunk/arch/blackfin/include/asm/bfin_sport.h (7871 => 7872)
--- trunk/arch/blackfin/include/asm/bfin_sport.h 2009-11-25 05:39:03 UTC (rev 7871)
+++ trunk/arch/blackfin/include/asm/bfin_sport.h 2009-11-25 06:48:10 UTC (rev 7872)
@@ -59,45 +59,60 @@
#ifdef __KERNEL__
+#include <linux/types.h>
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits. So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
struct sport_register {
- unsigned short tcr1;
- unsigned short reserved0;
- unsigned short tcr2;
- unsigned short reserved1;
- unsigned short tclkdiv;
- unsigned short reserved2;
- unsigned short tfsdiv;
- unsigned short reserved3;
- unsigned long tx;
- unsigned long reserved_l0;
- unsigned long rx;
- unsigned long reserved_l1;
- unsigned short rcr1;
- unsigned short reserved4;
- unsigned short rcr2;
- unsigned short reserved5;
- unsigned short rclkdiv;
- unsigned short reserved6;
- unsigned short rfsdiv;
- unsigned short reserved7;
- unsigned short stat;
- unsigned short reserved8;
- unsigned short chnl;
- unsigned short reserved9;
- unsigned short mcmc1;
- unsigned short reserved10;
- unsigned short mcmc2;
- unsigned short reserved11;
- unsigned long mtcs0;
- unsigned long mtcs1;
- unsigned long mtcs2;
- unsigned long mtcs3;
- unsigned long mrcs0;
- unsigned long mrcs1;
- unsigned long mrcs2;
- unsigned long mrcs3;
+ __BFP(tcr1);
+ __BFP(tcr2);
+ __BFP(tclkdiv);
+ __BFP(tfsdiv);
+ union {
+ u32 tx32;
+ u16 tx16;
+ };
+ u32 __pad_tx;
+ union {
+ u32 rx32; /* use the anomaly wrapper below */
+ u16 rx16;
+ };
+ u32 __pad_rx;
+ __BFP(rcr1);
+ __BFP(rcr2);
+ __BFP(rclkdiv);
+ __BFP(rfsdiv);
+ __BFP(stat);
+ __BFP(chnl);
+ __BFP(mcmc1);
+ __BFP(mcmc2);
+ u32 mtcs0;
+ u32 mtcs1;
+ u32 mtcs2;
+ u32 mtcs3;
+ u32 mrcs0;
+ u32 mrcs1;
+ u32 mrcs2;
+ u32 mrcs3;
};
+#undef __BFP
+#define bfin_read_sport_rx32(base) \
+({ \
+ struct sport_register *__mmrs = (void *)base; \
+ u32 __ret; \
+ unsigned long flags; \
+ if (ANOMALY_05000473) \
+ local_irq_save(flags); \
+ __ret = __mmrs->rx32; \
+ if (ANOMALY_05000473) \
+ local_irq_restore(flags); \
+ __ret; \
+})
+
#endif
/* SPORT_TCR1 Masks */
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