Modified: trunk/arch/blackfin/include/asm/cdef_misc.h (8262 => 8263)
--- trunk/arch/blackfin/include/asm/cdef_misc.h 2010-01-30 19:41:42 UTC (rev 8262)
+++ trunk/arch/blackfin/include/asm/cdef_misc.h 2010-02-01 06:07:24 UTC (rev 8263)
@@ -36,7 +36,7 @@
#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
-static __inline__ void bfin_iwr_set_pll(unsigned long *iwr0,
+static inline void bfin_iwr_set_pll(unsigned long *iwr0,
unsigned long *iwr1, unsigned long *iwr2)
{
#ifdef CONFIG_SMP
@@ -65,7 +65,7 @@
#if defined(CONFIG_HOTPLUG_CPU) || \
(defined(CONFIG_CPU_VOLTAGE) && defined(CONFIG_SMP))
-static __inline__ void bfin_iwr_set_sup0(unsigned long *iwr0,
+static inline void bfin_iwr_set_sup0(unsigned long *iwr0,
unsigned long *iwr1, unsigned long *iwr2)
{
#ifdef CONFIG_SMP
@@ -81,7 +81,7 @@
}
#endif
-static __inline__ void bfin_iwr_restore(unsigned long iwr0,
+static inline void bfin_iwr_restore(unsigned long iwr0,
unsigned long iwr1, unsigned long iwr2)
{
#ifdef CONFIG_SMP
@@ -105,7 +105,7 @@
}
/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+static inline void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags = 0;
unsigned long iwr0, iwr1, iwr2;
@@ -125,7 +125,7 @@
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
+static inline void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags = 0;
unsigned long iwr0, iwr1, iwr2;
