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[Linux-kernel-commits] [8706] trunk/sound/soc/codecs: task[#6004]clean up code

cliff Wed, 12 May 2010 03:08:46 -0700

Title: [8706] trunk/sound/soc/codecs: task[#6004]clean up code

Revision: 8706
Author: cliff
Date: 2010-05-12 06:10:11 -0400 (Wed, 12 May 2010)

Log Message

task[#6004]clean up code


Modified Paths

trunk/sound/soc/codecs/adau1373.c
trunk/sound/soc/codecs/adau1373.h

Diff

Modified: trunk/sound/soc/codecs/adau1373.c (8705 => 8706)


--- trunk/sound/soc/codecs/adau1373.c	2010-05-11 18:10:32 UTC (rev 8705)
+++ trunk/sound/soc/codecs/adau1373.c	2010-05-12 10:10:11 UTC (rev 8706)
@@ -326,47 +326,47 @@
 	case 0:
 		chip->in_chan_mask = CAP_INPA;
 		snd_soc_write(codec, ADAU_DMICCTL, 0x00);
-		snd_soc_write(codec, ADAU_LADCMIX, AIN1_SIGNAL_ENA);
-		snd_soc_write(codec, ADAU_RADCMIX, AIN1_SIGNAL_ENA);
+		snd_soc_write(codec, ADAU_LADCMIX, INPA_EN);
+		snd_soc_write(codec, ADAU_RADCMIX, INPA_EN);
 		snd_soc_write(codec, ADAU_IN1LCTL, cache[ADAU_IN1LCTL]);
 		snd_soc_write(codec, ADAU_IN1RCTL, cache[ADAU_IN1RCTL]);
 		/* Disable other ports */
 		snd_soc_write(codec, ADAU_PWDCTL1,
-			reg & ~(PWRCTLA_INBPD | PWRCTLA_INCPD | PWRCTLA_INDPD));
-		snd_soc_write(codec, ADAU_PWDCTL1, reg | PWRCTLA_INAPD);
+			reg & ~(AIN2PWR | AIN3PWR | AIN4PWR));
+		snd_soc_write(codec, ADAU_PWDCTL1, reg | AIN1PWR);
 		break;
 	case 1:
 		chip->in_chan_mask = CAP_INPB;
 		snd_soc_write(codec, ADAU_DMICCTL, 0x00);
-		snd_soc_write(codec, ADAU_LADCMIX, AIN2_SIGNAL_ENA);
-		snd_soc_write(codec, ADAU_RADCMIX, AIN2_SIGNAL_ENA);
+		snd_soc_write(codec, ADAU_LADCMIX, INPB_EN);
+		snd_soc_write(codec, ADAU_RADCMIX, INPB_EN);
 		snd_soc_write(codec, ADAU_IN2LCTL, cache[ADAU_IN2LCTL]);
 		snd_soc_write(codec, ADAU_IN2RCTL, cache[ADAU_IN2RCTL]);
 		snd_soc_write(codec, ADAU_PWDCTL1,
-			reg & ~(PWRCTLA_INAPD | PWRCTLA_INCPD | PWRCTLA_INDPD));
-		snd_soc_write(codec, ADAU_PWDCTL1, reg | PWRCTLA_INBPD);
+			reg & ~(AIN1PWR | AIN3PWR | AIN4PWR));
+		snd_soc_write(codec, ADAU_PWDCTL1, reg | AIN2PWR);
 		break;
 	case 2:
 		chip->in_chan_mask = CAP_INPC;
 		snd_soc_write(codec, ADAU_DMICCTL, 0x00);
-		snd_soc_write(codec, ADAU_LADCMIX, AIN3_SIGNAL_ENA);
-		snd_soc_write(codec, ADAU_RADCMIX, AIN3_SIGNAL_ENA);
+		snd_soc_write(codec, ADAU_LADCMIX, INPC_EN);
+		snd_soc_write(codec, ADAU_RADCMIX, INPC_EN);
 		snd_soc_write(codec, ADAU_IN3LCTL, cache[ADAU_IN3LCTL]);
 		snd_soc_write(codec, ADAU_IN3RCTL, cache[ADAU_IN3RCTL]);
 		snd_soc_write(codec, ADAU_PWDCTL1,
-			reg & ~(PWRCTLA_INAPD | PWRCTLA_INBPD | PWRCTLA_INDPD));
-		snd_soc_write(codec, ADAU_PWDCTL1, reg | PWRCTLA_INCPD);
+			reg & ~(AIN1PWR | AIN2PWR | AIN4PWR));
+		snd_soc_write(codec, ADAU_PWDCTL1, reg | AIN3PWR);
 		break;
 	case 3:
 		chip->in_chan_mask = CAP_INPD;
 		snd_soc_write(codec, ADAU_DMICCTL, 0x00);
-		snd_soc_write(codec, ADAU_LADCMIX, AIN4_SIGNAL_ENA);
-		snd_soc_write(codec, ADAU_RADCMIX, AIN4_SIGNAL_ENA);
+		snd_soc_write(codec, ADAU_LADCMIX, INPD_EN);
+		snd_soc_write(codec, ADAU_RADCMIX, INPD_EN);
 		snd_soc_write(codec, ADAU_AUXLCTL, cache[ADAU_AUXLCTL]);
 		snd_soc_write(codec, ADAU_AUXRCTL, cache[ADAU_AUXRCTL]);
 		snd_soc_write(codec, ADAU_PWDCTL1,
-			reg & ~(PWRCTLA_INAPD | PWRCTLA_INBPD | PWRCTLA_INCPD));
-		snd_soc_write(codec, ADAU_PWDCTL1, reg | PWRCTLA_INDPD);
+			reg & ~(AIN1PWR | AIN2PWR | AIN3PWR));
+		snd_soc_write(codec, ADAU_PWDCTL1, reg | AIN4PWR);
 		break;
 	case 4:
 		chip->in_chan_mask = CAP_DMIC;
@@ -430,8 +430,8 @@
 	switch (ucontrol->value.enumerated.item[0]) {
 	case 0:
 		chip->out_chan_mask = PB_LINE1;
-		snd_soc_write(codec, ADAU_LLN1MIX, LDAC_SIGNAL_ENA);
-		snd_soc_write(codec, ADAU_RLN1MIX, RDAC_SIGNAL_ENA);
+		snd_soc_write(codec, ADAU_LLN1MIX, DAC1_LEFT);
+		snd_soc_write(codec, ADAU_RLN1MIX, DAC1_RIGHT);
 		snd_soc_write(codec, ADAU_LLN1OPT, cache[ADAU_LLN1OPT]);
 		snd_soc_write(codec, ADAU_RLN1OPT, cache[ADAU_RLN1OPT]);
 		/* Disable other ports */
@@ -441,8 +441,8 @@
 		break;
 	case 1:
 		chip->out_chan_mask = PB_LINE2;
-		snd_soc_write(codec, ADAU_LLN2MIX, LDAC_SIGNAL_ENA);
-		snd_soc_write(codec, ADAU_RLN2MIX, RDAC_SIGNAL_ENA);
+		snd_soc_write(codec, ADAU_LLN2MIX, DAC1_LEFT);
+		snd_soc_write(codec, ADAU_RLN2MIX, DAC1_RIGHT);
 		snd_soc_write(codec, ADAU_LLN2OPT, cache[ADAU_LLN2OPT]);
 		snd_soc_write(codec, ADAU_RLN2OPT, cache[ADAU_RLN2OPT]);
 		snd_soc_write(codec, ADAU_PWDCTL2, reg0 & ~0x03);
@@ -451,8 +451,8 @@
 		break;
 	case 2:
 		chip->out_chan_mask = PB_SPK;
-		snd_soc_write(codec, ADAU_LCDMIX, LDAC_SIGNAL_ENA);
-		snd_soc_write(codec, ADAU_RCDMIX, RDAC_SIGNAL_ENA);
+		snd_soc_write(codec, ADAU_LCDMIX, DAC1_LEFT);
+		snd_soc_write(codec, ADAU_RCDMIX, DAC1_RIGHT);
 		snd_soc_write(codec, ADAU_LCDOUTP, cache[ADAU_LCDOUTP]);
 		snd_soc_write(codec, ADAU_RCDOUTP, cache[ADAU_RCDOUTP]);
 		snd_soc_write(codec, ADAU_PWDCTL2, reg0 & ~0x0F);
@@ -461,15 +461,15 @@
 		break;
 	case 3:
 		chip->out_chan_mask = PB_EARP;
-		snd_soc_write(codec, ADAU_EPMIX, LDAC_SIGNAL_ENA);
+		snd_soc_write(codec, ADAU_EPMIX, DAC1_LEFT);
 		snd_soc_write(codec, ADAU_PWDCTL2, reg0 & ~0x0F);
 		snd_soc_write(codec, ADAU_PWDCTL3, reg1 | 0x10);
 		snd_soc_write(codec, ADAU_PWDCTL3, reg1 & ~0x0E);
 		break;
 	case 4:
 		chip->out_chan_mask = PB_HP;
-		snd_soc_write(codec, ADAU_LHPMIX, LDAC_SIGNAL_ENA);
-		snd_soc_write(codec, ADAU_RHPMIX, RDAC_SIGNAL_ENA);
+		snd_soc_write(codec, ADAU_LHPMIX, DAC1_LEFT);
+		snd_soc_write(codec, ADAU_RHPMIX, DAC1_RIGHT);
 		snd_soc_write(codec, ADAU_LHPOUTP, cache[ADAU_LHPOUTP]);
 		snd_soc_write(codec, ADAU_RHPOUTP, cache[ADAU_RHPOUTP]);
 		snd_soc_write(codec, ADAU_PWDCTL2, reg0 & ~0x0F);
@@ -657,16 +657,16 @@
 	/* bit size */
 	switch (params_format(params)) {
 	case SNDRV_PCM_FORMAT_S16_LE:
-		dai_ctl = DAICTL_WLEN16;
+		dai_ctl = WLA_16;
 		break;
 	case SNDRV_PCM_FORMAT_S20_3LE:
-		dai_ctl = DAICTL_WLEN20;
+		dai_ctl = WLA_20;
 		break;
 	case SNDRV_PCM_FORMAT_S24_LE:
-		dai_ctl = DAICTL_WLEN24;
+		dai_ctl = WLA_24;
 		break;
 	case SNDRV_PCM_FORMAT_S32_LE:
-		dai_ctl = DAICTL_WLEN32;
+		dai_ctl = WLA_32;
 		break;
 	default:
 		dai_ctl = 0;
@@ -675,7 +675,7 @@
 	reg = snd_soc_read(codec, ADAU_DAIA);
 	snd_soc_write(codec, ADAU_DAIA, reg | dai_ctl);
 	snd_soc_write(codec, ADAU_PLLACTL, 0x00);
-	snd_soc_write(codec, ADAU_PLLACTL6, 0x01);
+	snd_soc_write(codec, ADAU_PLLACTL6, PLLEN);
 
 	return 0;
 }
@@ -693,7 +693,7 @@
 	do {
 		++counter;
 		schedule_timeout_interruptible(msecs_to_jiffies(1));
-	} while (((codec->hw_read(codec, ADAU_PLLACTL6)) & 0x04) == 0
+	} while (((codec->hw_read(codec, ADAU_PLLACTL6)) & PLL_LOCKED) == 0
 			&& counter < 20);
 	if (counter >= 20) {
 		dev_err(codec->dev, "failed to initialize PLL\n");
@@ -702,8 +702,7 @@
 	}
 
 	/* Use DAI A */
-	snd_soc_write(codec, ADAU_DAIACTL, 0x05);
-	snd_soc_write(codec, ADAU_DEEMPCTL, 0x11);
+	snd_soc_write(codec, ADAU_DAIACTL, DAI_EN);
 	reg = snd_soc_read(codec, ADAU_CLK1SDIV);
 	snd_soc_write(codec, ADAU_CLK1SDIV, reg | CLKSDIV_COREN);
 
@@ -735,11 +734,11 @@
 	reg0 = snd_soc_read(codec, ADAU_PWDCTL1);
 	reg1 = snd_soc_read(codec, ADAU_PWDCTL2);
 	if (mute) {
-		snd_soc_write(codec, ADAU_PWDCTL1, reg0 & ~0xc0);
-		snd_soc_write(codec, ADAU_PWDCTL2, reg1 & ~0x30);
+		snd_soc_write(codec, ADAU_PWDCTL1, reg0 & ~(LADCPWR | RADCPWR));
+		snd_soc_write(codec, ADAU_PWDCTL2, reg1 & ~(LDAC1PWR | RDAC1PWR));
 	} else {
-		snd_soc_write(codec, ADAU_PWDCTL1, reg0 | 0xc0);
-		snd_soc_write(codec, ADAU_PWDCTL2, reg1 | 0x30);
+		snd_soc_write(codec, ADAU_PWDCTL1, reg0 | LADCPWR | RADCPWR);
+		snd_soc_write(codec, ADAU_PWDCTL2, reg1 | LDAC1PWR | RDAC1PWR);
 	}
 	return 0;
 }
@@ -764,7 +763,7 @@
 	/* set master/slave audio interface */
 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 	case SND_SOC_DAIFMT_CBM_CFM:
-		dai_ctl |= 0x40;
+		dai_ctl |= MSA;
 		break;
 	case SND_SOC_DAIFMT_CBS_CFS:
 		break;
@@ -775,16 +774,16 @@
 	/* interface format */
 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 	case SND_SOC_DAIFMT_I2S:
-		dai_ctl |= 0x02;
+		dai_ctl |= FORMAT_I2S;
 		break;
 	case SND_SOC_DAIFMT_RIGHT_J:
-		dai_ctl |= 0x00;
+		dai_ctl |= FORMAT_RJUST;
 		break;
 	case SND_SOC_DAIFMT_LEFT_J:
-		dai_ctl |= 0x01;
+		dai_ctl |= FORMAT_LJUST;
 		break;
 	case SND_SOC_DAIFMT_DSP_B:
-		dai_ctl |= 0x03;
+		dai_ctl |= FORMAT_DSP;
 		break;
 	default:
 		return -EINVAL;
@@ -795,13 +794,13 @@
 	case SND_SOC_DAIFMT_NB_NF:
 		break;
 	case SND_SOC_DAIFMT_IB_IF:
-		dai_ctl |= 0x90;
+		dai_ctl |= LRPA_INV | BCLK_INV;
 		break;
 	case SND_SOC_DAIFMT_IB_NF:
-		dai_ctl |= 0x80;
+		dai_ctl |= BCLK_INV;
 		break;
 	case SND_SOC_DAIFMT_NB_IF:
-		dai_ctl |= 0x10;
+		dai_ctl |= LRPA_INV;
 		break;
 	default:
 		return -EINVAL;
@@ -822,7 +821,7 @@
 	reg_clk = snd_soc_read(codec, ADAU_CLK1SDIV);
 	switch (level) {
 	case SND_SOC_BIAS_ON:
-		snd_soc_write(codec, ADAU_PWDCTL3, reg_pwr | 0x01);
+		snd_soc_write(codec, ADAU_PWDCTL3, reg_pwr | WHOLEPWR);
 		snd_soc_write(codec, ADAU_CLK1SDIV, reg_clk | CLKSDIV_COREN);
 		/* vref/mid, osc on, dac unmute */
 		break;
@@ -833,7 +832,7 @@
 		snd_soc_write(codec, ADAU_CLK1SDIV, reg_clk & ~CLKSDIV_COREN);
 		break;
 	case SND_SOC_BIAS_OFF:
-		snd_soc_write(codec, ADAU_PWDCTL3, reg_pwr & ~0x01);
+		snd_soc_write(codec, ADAU_PWDCTL3, reg_pwr & ~WHOLEPWR);
 		snd_soc_write(codec, ADAU_CLK1SDIV, reg_clk & ~CLKSDIV_COREN);
 		break;
 	}
@@ -976,7 +975,7 @@
 	/* Capture settings */
 #if DIGMIC
 	/* Digital microphone A */
-	snd_soc_write(codec, ADAU_DMICCTL, 0x01);
+	snd_soc_write(codec, ADAU_DMICCTL, DMICAEN);
 #else
 	snd_soc_write(codec, ADAU_INPMODE, 0x00);
 	/* Input volume gain: 0 db */
@@ -990,8 +989,8 @@
 	snd_soc_write(codec, ADAU_AUXRCTL, 0x0D);
 
 	/* AIN1 enabled */
-	snd_soc_write(codec, ADAU_LADCMIX, 0x01);
-	snd_soc_write(codec, ADAU_RADCMIX, 0x01);
+	snd_soc_write(codec, ADAU_LADCMIX, INPA_EN);
+	snd_soc_write(codec, ADAU_RADCMIX, INPA_EN);
 
 	snd_soc_write(codec, ADAU_MICCTR1, 0x00);
 	snd_soc_write(codec, ADAU_EPCNTRL, 0x0C);
@@ -999,34 +998,36 @@
 	/* Playback settings*/
 
 	/* Headphone enabled */
-	snd_soc_write(codec, ADAU_LHPMIX, 0x20);
-	snd_soc_write(codec, ADAU_RHPMIX, 0x20);
+	snd_soc_write(codec, ADAU_LHPMIX, DAC1_RIGHT);
+	snd_soc_write(codec, ADAU_RHPMIX, DAC1_RIGHT);
 
-	snd_soc_write(codec, ADAU_HPCTRL, 0x10);
-	snd_soc_write(codec, ADAU_HPCTRL2, 0x20);
+	snd_soc_write(codec, ADAU_HPCTRL, POPTIME4M);
+	snd_soc_write(codec, ADAU_HPCTRL2, LVLTHR400);
 	/* 0db */
 	snd_soc_write(codec, ADAU_LHPOUTP, 0x1F);
 	snd_soc_write(codec, ADAU_RHPOUTP, 0x1F);
 
-	/* clock souce: PLL1, FS, 64 bits per frame */
-	snd_soc_write(codec, ADAU_BCLKDIVA, 0x02);
+	/* clock souce: CLK1, FS, 64 bits per frame */
+	snd_soc_write(codec, ADAU_BCLKDIVA, BPFA_64);
 
-	snd_soc_write(codec, ADAU_DINMIXC0, 0x01);
-	snd_soc_write(codec, ADAU_DOPMIXC3, 0x01);
+	/* Playback: Channel 0, DAIA --> DAC */
+	snd_soc_write(codec, ADAU_DINMIXC0, DIN_AIFAPB);
+	snd_soc_write(codec, ADAU_DOPMIXC3, DOUT_CH0_DAC);
+	/* Capture: Channel 1, ADC --> DAIA */
+	snd_soc_write(codec, ADAU_DINMIXC1, DIN_ADC);
+	snd_soc_write(codec, ADAU_DOPMIXC0, DOUT_CH1_REC);
 
-	snd_soc_write(codec, ADAU_DINMIXC1, 0x08);
-	snd_soc_write(codec, ADAU_DOPMIXC0, 0x02);
 	/* PWR on input port A, MIC1 BIAS, right and left ADCs */
-	reg = 0xB1;
+	reg = AIN1PWR | MICB1PWR | RADCPWR | LADCPWR;
 	snd_soc_write(codec, ADAU_PWDCTL1, reg);
 	/* PWR on right and left 0f DAC1 */
-	reg = 0x30;
+	reg = RDAC1PWR | LDAC1PWR;
 	snd_soc_write(codec, ADAU_PWDCTL2, reg);
-	reg = 0x03;
+	reg = WHOLEPWR | HPPWR;
 	snd_soc_write(codec, ADAU_PWDCTL3, reg);
 
 	/* Enable playback, capture */
-	snd_soc_write(codec, ADAU_DIGEN, 0x05);
+	snd_soc_write(codec, ADAU_DIGEN, PBAEN | RECEN);
 	snd_soc_write(codec, 0x3C, 0x07);
 	snd_soc_write(codec, 0x3C, 0x05);

Modified: trunk/sound/soc/codecs/adau1373.h (8705 => 8706)


--- trunk/sound/soc/codecs/adau1373.h	2010-05-11 18:10:32 UTC (rev 8705)
+++ trunk/sound/soc/codecs/adau1373.h	2010-05-12 10:10:11 UTC (rev 8706)
@@ -125,7 +125,6 @@
 #define ADAU_DCPBLVOL	0x66
 #define ADAU_DCPBRVOL	0x67
 
-
 #define ADAU_DARCLVOL	0x68
 #define ADAU_DARCRVOL	0x69
 #define ADAU_DBRCLVOL	0x6A
@@ -178,82 +177,149 @@
  * (Mask value to extract the corresponding Register field)
  */
 
-#define VOL_MASK		0x1F
-#define AIN1_SIGNAL_ENA		0x01
-#define AIN2_SIGNAL_ENA		0x02
-#define AIN3_SIGNAL_ENA		0x04
-#define AIN4_SIGNAL_ENA		0x08
-#define LDAC_SIGNAL_ENA		0x10
-#define RDAC_SIGNAL_ENA		0x20
+/* ADC_GAIN */
+#define ADCLGAIN0	0x01
+#define ADCLGAIN1	0x02
+#define ADCLGAIN2	0x04
+#define ADCLGAIN3	0x08
+#define ADCRGAIN0	0x10
+#define ADCRGAIN1	0x20
+#define ADCRGAIN2	0x40
+#define ADCRGAIN3	0x80
 
-/* PWR Management */
-#define PWRCTLA_INAPD		0x01
-#define PWRCTLA_INBPD		0x02
-#define PWRCTLA_INCPD		0x04
-#define PWRCTLA_INDPD		0x08
-#define PWRCTLA_PASSPD		0x10
-#define PWRCTLA_MICBPD		0x20
-#define PWRCTLA_LADCPD		0x40
-#define PWRCTLA_RADCPD		0x80
+/* INPUT MIX */
+#define INPA_EN		0x01
+#define INPB_EN		0x02
+#define INPC_EN		0x04
+#define INPD_EN		0x08
+#define DAC1_LEFT	0x10
+#define DAC1_RIGHT	0x20
+#define DAC2_LEFT	0x40
+#define DAC2_RIGHT	0x80
 
-#define PWRCTLB_PWDB		0x01
-#define PWRCTLB_HPPD		0x02
-#define PWRCTLB_LCDPD		0x04
-#define PWRCTLB_RCDPD		0x08
-#define PWRCTLB_LDACPD		0x10
-#define PWRCTLB_RDACPD		0x20
-#define PWRCTLB_LLNPD		0x40
-#define PWRCTLB_RLNPD		0x80
+/* HP_CTRL */
+#define POPTIME2M	0x00
+#define POPTIME4M	0x10
+#define POPTIME8M	0x20
+#define POPTIME16M	0x30
+#define HPMODECLAG	0x00
+#define HPMODEHELO	0x04
+#define HPMODELEHO	0x08
+#define HPOCL1		0x00
+#define HPOCL2		0x01
+#define HPOCL3		0x02
+#define HPOCL4		0x03
 
-/* PLL Control */
+/* HP_CTRL2 */
+#define VOLLIMEN_MON	0x01
+#define LVLTHR300	0x00
+#define LVLTHR400	0x20
+#define LVLTHR500	0x40
 
-#define PLLCTLA_X_SHIFT		1
-#define PLLCTLA_R_SHIFT		3
-#define PLLCTLB_PLLEN		0x01	/* PLL enable */
-#define PLLCTLB_LOCK		0x20	/* Lock poll */
+/* PWDN_CTRL1 */
+#define AIN1PWR		0x01
+#define AIN2PWR		0x02
+#define AIN3PWR		0x04
+#define AIN4PWR		0x08
+#define MICB1PWR	0x10
+#define MICB2PWR	0x20
+#define RADCPWR		0x40
+#define LADCPWR		0x80
 
-/*Clock GEN*/
+/* PWDN_CTRL2 */
+#define LLN1PWR		0x01
+#define RLN1PWR		0x02
+#define LLN2PWR		0x04
+#define RLN2PWR		0x08
+#define RDAC1PWR	0x10
+#define LDAC1PWR	0x20
+#define LDAC2PWR	0x40
+#define RDAC2PWR	0x80
 
-#define CLKSDIV_COREN		0x80	/* Core clock enable */
-#define CLKSDIV_PLL_BYPASS	0x40	/* Bypass PLL */
-#define CLKSDIV_CLKDIV_SHIFT	3
-#define CLKSDIV_MCLKDIV_SHIFT	0
+/* PWDN_CTRL3 */
+#define WHOLEPWR	0x01
+#define HPPWR		0x02
+#define RCDPWR		0x04
+#define LCDPWR		0x08
+#define EPPWR		0x10
+#define BSTPWR	0x20
+#define ZDPWR	0x40
 
-/* DAI Control */
+/* PLL_CTRL6 */
+#define PLLEN		0x01
+#define DPLL_BYPASS	0x02
+#define PLL_LOCKED	0x04
+#define DPLL_LOCKED	0x08
 
-#define DAICTL_FMRJUST		0x00	/* Audio interface mode */
-#define DAICTL_FMLJUST		0x01
-#define DAICTL_FMI2S		0x02
-#define DAICTL_FMDSP		0x03
+/* CLK1SDIV */
+#define CLKSDIV_COREN	0x80
+#define CLKSDIV_CLKDIV_SHIFT 3
+/* DAIA */
+#define FORMAT_RJUST	0x00
+#define FORMAT_LJUST	0x01
+#define FORMAT_I2S	0x02
+#define FORMAT_DSP	0x03
 
-#define DAICTL_WLEN16		0x00	/* Word length */
-#define DAICTL_WLEN20		0x04
-#define DAICTL_WLEN24		0x08
-#define DAICTL_WLEN32		0x0c
+#define WLA_16		0x00
+#define WLA_20		0x04
+#define WLA_24		0x08
+#define WLA_32		0x0C
 
-#define DAICTL_LRPA		0x10
-#define DAICTL_SWAPA		0x20
-#define DAICTL_MSA		0x40	/* Codec in master mode */
-#define DAICTL_BLKINVA		0x80
+#define LRPA_INV	0x10
+#define SWAPA		0x20
+#define MSA		0x40
+#define BCLK_INV	0x80
 
-/* Number of bit clock per frame */
-#define BCLKDIV_BPFA256		0x00
-#define BCLKDIV_BPFA128		0x01
-#define BCLKDIV_BPFA64		0x02
-#define BCLKDIV_BPFA32		0x03
+/* BCLKDIVA */
+#define BPFA_256	0x00
+#define BPFA_128	0x01
+#define BPFA_64		0x02
+#define BPFA_32		0x03
 
-/* SRC/DAI Control */
-#define SRCDAICTL_DAIA_ENA	0x01
-#define SRCDAICTL_DAIB_ENA	0x02
-#define SRCDAICTL_SRCREC_ENA	0x04
-#define SRCDAICTL_SRCPB_ENA	0x08
-/* DIGMIC */
-#define DIGMIC_EN		0x01
+#define DAISR_FS	0x00
+#define DAISRC_CLK2	0x20
+
+/* DAI_CTRL*/
+#define DAI_EN		0x01
+
+/* DIN_MIX_CTRL */
+#define DIN_AIFAPB	0x01
+#define DIN_AIFBPB	0x02
+#define DIN_AIFCPB	0x04
+#define DIN_ADC		0x08
+#define DIN_ADCSWP	0x10
+#define DIN_DMIC	0x20
+#define DIN_DMICSWP	0x40
+
+/* DOUT_MIX_CTRL */
+#define DOUT_CH0_REC	0x01
+#define DOUT_CH1_REC	0x02
+#define DOUT_CH2_REC	0x04
+#define DOUT_CH3_REC	0x08
+#define DOUT_CH4_REC	0x10
+
+/* DOUT_MIX_CTRL_DAC */
+#define DOUT_CH0_DAC	0x01
+#define DOUT_CH1_DAC	0x02
+#define DOUT_CH2_DAC	0x04
+#define DOUT_CH3_DAC	0x08
+#define DOUT_CH4_DAC	0x10
+
+/* DIGMIC_CTRL*/
+#define DMICAEN		0x01
+#define DMICASWP	0x02
+#define DMICBEN		0x04
+#define DMICBSWP	0x08
+#define DMIC2MONO	0x80
+
 /* DIGEN */
-#define DIGEN_PBEN		0x01
-#define DIGEN_RECEN		0x02
-#define DIGEN_FDSPEN		0x04
+#define PBAEN		0x01
+#define PBBEN		0x02
+#define RECEN		0x04
+#define DRECEN		0x08
+#define FDSPEN		0x10
 
+
 #define PB_LINE1		0x01
 #define PB_LINE2		0x02
 #define PB_SPK			0x04

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