Title: [8860] trunk/arch/blackfin: bfin: allow cache funcs to be in L1 for anomaly 491
- Revision
- 8860
- Author
- vapier
- Date
- 2010-05-27 18:46:46 -0400 (Thu, 27 May 2010)
Log Message
bfin: allow cache funcs to be in L1 for anomaly 491
Modified Paths
Diff
Modified: trunk/arch/blackfin/Kconfig (8859 => 8860)
--- trunk/arch/blackfin/Kconfig 2010-05-27 22:40:26 UTC (rev 8859)
+++ trunk/arch/blackfin/Kconfig 2010-05-27 22:46:46 UTC (rev 8860)
@@ -853,6 +853,18 @@
If enabled, the CPLB Switch Tables are linked
into L1 data memory. (less latency)
+config CACHE_FLUSH_L1
+ bool "Locate cache flush funcs in L1 Inst Memory"
+ default y
+ help
+ If enabled, the Blackfin cache flushing functions are linked
+ into L1 instruction memory.
+
+ Note that this might be required to address anomalies, but
+ these functions are pretty small, so it shouldn't be too bad.
+ If you are using a processor affected by an anomaly, the build
+ system will double check for you and prevent it.
+
config APP_STACK_L1
bool "Support locating application stack in L1 Scratch Memory"
default y
Modified: trunk/arch/blackfin/mach-common/cache.S (8859 => 8860)
--- trunk/arch/blackfin/mach-common/cache.S 2010-05-27 22:40:26 UTC (rev 8859)
+++ trunk/arch/blackfin/mach-common/cache.S 2010-05-27 22:46:46 UTC (rev 8860)
@@ -11,7 +11,11 @@
#include <asm/cache.h>
#include <asm/page.h>
+#ifdef CONFIG_CACHE_FLUSH_L1
+.section .l1.text
+#else
.text
+#endif
/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
#if ANOMALY_05000443
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