Diff
Modified: trunk/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h (9022 => 9023)
--- trunk/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h 2010-07-28 19:54:58 UTC (rev 9022)
+++ trunk/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h 2010-07-28 19:59:03 UTC (rev 9023)
@@ -1147,7 +1147,7 @@
#define TWI_ENA 0x0080 /* TWI Enable */
#define SCCB 0x0200 /* SCCB Compatibility Enable */
-/* TWI_SLAVE_CTRL Masks */
+/* TWI_SLAVE_CTL Masks */
#define SEN 0x0001 /* Slave Enable */
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
@@ -1158,7 +1158,7 @@
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
#define GCALL 0x0002 /* General Call Indicator */
-/* TWI_MASTER_CTRL Masks */
+/* TWI_MASTER_CTL Masks */
#define MEN 0x0001 /* Master Mode Enable */
#define MADD_LEN 0x0002 /* Master Address Length */
#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
Modified: trunk/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h (9022 => 9023)
--- trunk/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h 2010-07-28 19:54:58 UTC (rev 9022)
+++ trunk/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h 2010-07-28 19:59:03 UTC (rev 9023)
@@ -1156,7 +1156,7 @@
#define TWI_ENA 0x0080 /* TWI Enable */
#define SCCB 0x0200 /* SCCB Compatibility Enable */
-/* TWI_SLAVE_CTRL Masks */
+/* TWI_SLAVE_CTL Masks */
#define SEN 0x0001 /* Slave Enable */
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
@@ -1167,7 +1167,7 @@
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
#define GCALL 0x0002 /* General Call Indicator */
-/* TWI_MASTER_CTRL Masks */
+/* TWI_MASTER_CTL Masks */
#define MEN 0x0001 /* Master Mode Enable */
#define MADD_LEN 0x0002 /* Master Address Length */
#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
Modified: trunk/arch/blackfin/mach-bf537/include/mach/defBF534.h (9022 => 9023)
--- trunk/arch/blackfin/mach-bf537/include/mach/defBF534.h 2010-07-28 19:54:58 UTC (rev 9022)
+++ trunk/arch/blackfin/mach-bf537/include/mach/defBF534.h 2010-07-28 19:59:03 UTC (rev 9023)
@@ -1476,7 +1476,7 @@
#define TWI_ENA 0x0080 /* TWI Enable */
#define SCCB 0x0200 /* SCCB Compatibility Enable */
-/* TWI_SLAVE_CTRL Masks */
+/* TWI_SLAVE_CTL Masks */
#define SEN 0x0001 /* Slave Enable */
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
@@ -1487,7 +1487,7 @@
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
#define GCALL 0x0002 /* General Call Indicator */
-/* TWI_MASTER_CTRL Masks */
+/* TWI_MASTER_CTL Masks */
#define MEN 0x0001 /* Master Mode Enable */
#define MADD_LEN 0x0002 /* Master Address Length */
#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
Modified: trunk/arch/blackfin/mach-bf538/include/mach/defBF539.h (9022 => 9023)
--- trunk/arch/blackfin/mach-bf538/include/mach/defBF539.h 2010-07-28 19:54:58 UTC (rev 9022)
+++ trunk/arch/blackfin/mach-bf538/include/mach/defBF539.h 2010-07-28 19:59:03 UTC (rev 9023)
@@ -442,10 +442,10 @@
/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
-#define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */
+#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */
+#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
@@ -761,10 +761,10 @@
/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
-#define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */
+#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
-#define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */
+#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */
#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
Modified: trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h (9022 => 9023)
--- trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h 2010-07-28 19:54:58 UTC (rev 9022)
+++ trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h 2010-07-28 19:59:03 UTC (rev 9023)
@@ -60,10 +60,10 @@
#define TWI1_REGBASE 0xffc02200
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
Modified: trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h (9022 => 9023)
--- trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h 2010-07-28 19:54:58 UTC (rev 9022)
+++ trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h 2010-07-28 19:59:03 UTC (rev 9023)
@@ -99,10 +99,10 @@
#define TWI1_REGBASE 0xffc02200
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
Modified: trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h (9022 => 9023)
--- trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h 2010-07-28 19:54:58 UTC (rev 9022)
+++ trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h 2010-07-28 19:59:03 UTC (rev 9023)
@@ -105,10 +105,10 @@
#define TWI0_REGBASE 0xffc00700
#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */
#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */
#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
