Title: [9025] trunk/arch/blackfin/mach-bf548/include/mach: bf54x: use TWI_FIFO_CTL rather than xxx_CTRL and tweak DMAC MMR style to match other ports
- Revision
- 9025
- Author
- vapier
- Date
- 2010-07-28 22:04:42 -0400 (Wed, 28 Jul 2010)
Log Message
bf54x: use TWI_FIFO_CTL rather than xxx_CTRL and tweak DMAC MMR style to match other ports
Modified Paths
Diff
Modified: trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h (9024 => 9025)
--- trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h 2010-07-28 20:00:52 UTC (rev 9024)
+++ trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h 2010-07-29 02:04:42 UTC (rev 9025)
@@ -299,10 +299,10 @@
/* DMAC0 Registers */
-#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
+#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
+#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
+#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
+#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
/* DMA Channel 0 Registers */
@@ -1153,10 +1153,10 @@
/* DMAC1 Registers */
-#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
+#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
+#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
+#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
+#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
/* DMA Channel 12 Registers */
Modified: trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h (9024 => 9025)
--- trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h 2010-07-28 20:00:52 UTC (rev 9024)
+++ trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h 2010-07-29 02:04:42 UTC (rev 9025)
@@ -68,7 +68,7 @@
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
Modified: trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h (9024 => 9025)
--- trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h 2010-07-28 20:00:52 UTC (rev 9024)
+++ trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h 2010-07-29 02:04:42 UTC (rev 9025)
@@ -107,7 +107,7 @@
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
Modified: trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h (9024 => 9025)
--- trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h 2010-07-28 20:00:52 UTC (rev 9024)
+++ trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h 2010-07-29 02:04:42 UTC (rev 9025)
@@ -113,7 +113,7 @@
#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */
#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
@@ -198,8 +198,8 @@
/* DMAC0 Registers */
-#define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
+#define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
/* DMA Channel 0 Registers */
@@ -688,8 +688,8 @@
/* DMAC1 Registers */
-#define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
+#define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
/* DMA Channel 12 Registers */
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