Title: [9127] trunk/arch/blackfin: [#6190] bf561 smp: fix commit 9122 link coreb_trampoline_start to .l1.text
- Revision
- 9127
- Author
- steven.miao
- Date
- 2010-09-07 06:08:36 -0400 (Tue, 07 Sep 2010)
Log Message
[#6190] bf561 smp: fix commit 9122 link coreb_trampoline_start to .l1.text
link coreb_trampoline_start to .l1.text section instead of add offset 0x200
to relocate l1 mem. defer bfin_setup_caches(cpu) to avoid unexpected fault.
Modified Paths
Diff
Modified: trunk/arch/blackfin/kernel/setup.c (9126 => 9127)
--- trunk/arch/blackfin/kernel/setup.c 2010-09-07 03:48:22 UTC (rev 9126)
+++ trunk/arch/blackfin/kernel/setup.c 2010-09-07 10:08:36 UTC (rev 9127)
@@ -230,9 +230,11 @@
unsigned long data_l1_len = (unsigned long)_data_l1_len;
unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
+ blackfin_dma_early_init();
+
/* if necessary, copy L1 text to L1 instruction SRAM */
if (L1_CODE_LENGTH && text_l1_len)
- early_dma_memcpy((void *)COREB_L1_CODE_START + 0x200, _text_l1_lma,
+ early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
text_l1_len);
/* if necessary, copy L1 data to L1 data bank A SRAM */
@@ -245,9 +247,10 @@
early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma,
data_b_l1_len);
+ early_dma_memcpy_done();
#if ANOMALY_05000491
blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 -
- (unsigned long)_stext_l1 + COREB_L1_CODE_START + 0x200;
+ (unsigned long)_stext_l1 + COREB_L1_CODE_START;
#endif
}
#endif
Modified: trunk/arch/blackfin/kernel/vmlinux.lds.S (9126 => 9127)
--- trunk/arch/blackfin/kernel/vmlinux.lds.S 2010-09-07 03:48:22 UTC (rev 9126)
+++ trunk/arch/blackfin/kernel/vmlinux.lds.S 2010-09-07 10:08:36 UTC (rev 9127)
@@ -176,6 +176,10 @@
{
. = ALIGN(4);
__stext_l1 = .;
+#ifdef CONFIG_SMP
+ *(.l1.text.secondary)
+ . = ALIGN(4);
+#endif
*(.l1.text)
#ifdef CONFIG_SCHEDULE_L1
SCHED_TEXT
Modified: trunk/arch/blackfin/mach-bf561/secondary.S (9126 => 9127)
--- trunk/arch/blackfin/mach-bf561/secondary.S 2010-09-07 03:48:22 UTC (rev 9126)
+++ trunk/arch/blackfin/mach-bf561/secondary.S 2010-09-07 10:08:36 UTC (rev 9127)
@@ -13,7 +13,7 @@
#include <asm/asm-offsets.h>
#include <asm/trace.h>
-__INIT
+.section .l1.text.secondary
/* Lay the initial stack into the L1 scratch area of Core B */
#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
Modified: trunk/arch/blackfin/mach-bf561/smp.c (9126 => 9127)
--- trunk/arch/blackfin/mach-bf561/smp.c 2010-09-07 03:48:22 UTC (rev 9126)
+++ trunk/arch/blackfin/mach-bf561/smp.c 2010-09-07 10:08:36 UTC (rev 9127)
@@ -32,11 +32,10 @@
{
int len;
- len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
+ len = &coreb_trampoline_end - &coreb_trampoline_start;
BUG_ON(len > L1_CODE_LENGTH);
- dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
-
+ bfin_relocate_coreb_l1_mem();
/* Both cores ought to be present on a bf561! */
cpu_set(0, cpu_present_map); /* CoreA */
cpu_set(1, cpu_present_map); /* CoreB */
@@ -107,8 +106,6 @@
/* release the lock and let coreb run */
spin_unlock(&boot_lock);
- bfin_relocate_coreb_l1_mem();
-
return 0;
} else
panic("CPU%u: processor failed to boot\n", cpu);
Modified: trunk/arch/blackfin/mach-common/smp.c (9126 => 9127)
--- trunk/arch/blackfin/mach-common/smp.c 2010-09-07 03:48:22 UTC (rev 9126)
+++ trunk/arch/blackfin/mach-common/smp.c 2010-09-07 10:08:36 UTC (rev 9127)
@@ -369,8 +369,6 @@
*/
init_exception_vectors();
- bfin_setup_caches(cpu);
-
local_irq_disable();
/* Attach the new idle task to the global mm. */
@@ -389,6 +387,7 @@
local_irq_enable();
+ bfin_setup_caches(cpu);
/*
* Calibrate loops per jiffy value.
* IRQs need to be enabled here - D-cache can be invalidated
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