Title: [9618] trunk/sound/soc: [!no_src_qa!]
- Revision
- 9618
- Author
- scott
- Date
- 2011-02-16 05:18:16 -0500 (Wed, 16 Feb 2011)
Log Message
[!no_src_qa!]
asoc: ad74111 driver update to 2.6.37
Modified Paths
Diff
Modified: trunk/sound/soc/blackfin/Kconfig (9617 => 9618)
--- trunk/sound/soc/blackfin/Kconfig 2011-02-16 03:55:09 UTC (rev 9617)
+++ trunk/sound/soc/blackfin/Kconfig 2011-02-16 10:18:16 UTC (rev 9618)
@@ -18,7 +18,7 @@
Say Y if you want to add support for SoC audio on BF527-EZKIT.
config SND_BF5XX_SOC_AD73311
- tristate "SoC AD73311 Audio support for Blackfin"
+ tristate "SoC AD73311/AD74111 Audio support for Blackfin"
depends on SND_BF5XX_I2S
select SND_BF5XX_SOC_I2S
select SND_SOC_AD73311
@@ -33,6 +33,21 @@
Enter the GPIO used to control AD73311's SE pin. Acceptable
values are 0 to 7
+config SND_BFIN_AD73311_RESET
+ int "RESET pin for AD73311L Chip Select"
+ depends on SND_BF5XX_SOC_AD73311
+ default 4
+ help
+ Enter the GPIO used to control AD73311's RESET pin. Acceptable
+ values are 0 to 7
+
+config SND_AD7XXXX_SELECT
+ int "Select AD73311 or AD74111"
+ depends on SND_SOC_AD73311
+ default 0
+ help
+ Set 0 for AD73311, 1 for AD74111.
+
config SND_BF5XX_SOC_ADAU1361
tristate "SoC ADAU1361 Audio support"
depends on SND_BF5XX_I2S
Modified: trunk/sound/soc/blackfin/bf5xx-ad73311.c (9617 => 9618)
--- trunk/sound/soc/blackfin/bf5xx-ad73311.c 2011-02-16 03:55:09 UTC (rev 9617)
+++ trunk/sound/soc/blackfin/bf5xx-ad73311.c 2011-02-16 10:18:16 UTC (rev 9618)
@@ -63,24 +63,33 @@
#endif
#define GPIO_SE CONFIG_SND_BFIN_AD73311_SE
+#define GPIO_RESET CONFIG_SND_BFIN_AD73311_RESET
static struct snd_soc_card bf5xx_ad73311;
-static int snd_ad73311_startup(void)
+static void snd_ad73311_reset(void)
{
+ gpio_set_value(GPIO_RESET, 0);
+ udelay(100);
+ gpio_set_value(GPIO_RESET, 1);
+}
+
+static void snd_ad73311_startup(void)
+{
pr_debug("%s enter\n", __func__);
/* Pull up SE pin on AD73311L */
gpio_set_value(GPIO_SE, 1);
- return 0;
+ udelay(1);
}
static int snd_ad73311_configure(void)
{
- unsigned short ctrl_regs[6];
+ unsigned short ctrl_regs[7];
unsigned short status = 0;
int count = 0;
+#if CONFIG_SND_AD7XXXX_SELECT == 0
/* DMCLK = MCLK = 16.384 MHz
* SCLK = DMCLK/8 = 2.048 MHz
* Sample Rate = DMCLK/2048 = 8 KHz
@@ -94,10 +103,26 @@
ctrl_regs[3] = AD_CONTROL | AD_WRITE | CTRL_REG_E | REGE_DA(0x1f);
ctrl_regs[4] = AD_CONTROL | AD_WRITE | CTRL_REG_F | REGF_SEEN ;
ctrl_regs[5] = AD_CONTROL | AD_WRITE | CTRL_REG_A | REGA_MODE_DATA;
-
+#elif CONFIG_SND_AD7XXXX_SELECT == 1
+ /* MCLK = MCLK = 12.288 MHz
+ * Sample Rate = 8 KHz
+ * IMCLK = MCLK/6 = 2.048 MHz = 8kHz * 256
+ */
+ ctrl_regs[0] = AD_WRITE | CTRL_REG_A | REGA_REFAMP | REGA_REF |\
+ REGA_DAC | REGA_ADC_INPAMP;
+ ctrl_regs[1] = AD_WRITE | CTRL_REG_B | REGB_FCLKDIV(2) | \
+ REGB_SCLKDIV(1) | REGB_TCLKDIV(0);
+ ctrl_regs[2] = AD_WRITE | CTRL_REG_C | REGC_ADC_HP | \
+ REGC_WORD_WIDTH(0);
+ ctrl_regs[3] = AD_WRITE | CTRL_REG_D | REGD_MASTER | \
+ REGD_FDCLK | REGD_DSP_MODE;
+ ctrl_regs[4] = AD_WRITE | CTRL_REG_E;
+ ctrl_regs[5] = AD_WRITE | CTRL_REG_F;
+ ctrl_regs[6] = AD_WRITE | CTRL_REG_G;
+#endif
local_irq_disable();
+ snd_ad73311_reset();
snd_ad73311_startup();
- udelay(1);
bfin_write_SPORT_TCR1(TFSR);
bfin_write_SPORT_TCR2(0xF);
@@ -137,7 +162,16 @@
return -EBUSY;
}
+ if (GPIO_SE != GPIO_RESET) {
+ if (gpio_request(GPIO_RESET, "AD73311_RESET")) {
+ printk(KERN_ERR "%s: Failed ro request GPIO_%d\n", __func__, GPIO_RESET);
+ gpio_free(GPIO_SE);
+ return -EBUSY;
+ }
+ }
+
gpio_direction_output(GPIO_SE, 0);
+ gpio_direction_output(GPIO_RESET, 0);
err = snd_ad73311_configure();
if (err < 0)
Modified: trunk/sound/soc/codecs/ad73311.h (9617 => 9618)
--- trunk/sound/soc/codecs/ad73311.h 2011-02-16 03:55:09 UTC (rev 9617)
+++ trunk/sound/soc/codecs/ad73311.h 2011-02-16 10:18:16 UTC (rev 9618)
@@ -31,6 +31,8 @@
#ifndef __AD73311_H__
#define __AD73311_H__
+#if CONFIG_SND_AD7XXXX_SELECT == 0
+
#define AD_CONTROL 0x8000
#define AD_DATA 0x0000
#define AD_READ 0x4000
@@ -85,4 +87,58 @@
#define REGF_INV (1 << 6)
#define REGF_ALB (1 << 7)
+#elif CONFIG_SND_AD7XXXX_SELECT == 1
+
+#define AD_READ 0x0000
+#define AD_WRITE 0x8000
+
+/* Control register A */
+#define CTRL_REG_A (0 << 11)
+
+#define REGA_REFAMP (1 << 2)
+#define REGA_REF (1 << 3)
+#define REGA_DAC (1 << 4)
+#define REGA_ADC (1 << 5)
+#define REGA_ADC_INPAMP (1 << 6)
+
+/* Control register B */
+#define CTRL_REG_B (1 << 11)
+
+#define REGB_FCLKDIV(x) (x & 0x3)
+#define REGB_SCLKDIV(x) ((x & 0x3) << 2)
+#define REGB_TCLKDIV(x) ((x & 0x3) << 4)
+
+/* Control register C */
+#define CTRL_REG_C (2 << 11)
+
+#define REGC_ADC_HP (1 << 0)
+#define REGC_DAC_DEEMPH(x) ((x & 0x3) << 1)
+#define REGC_LG_DELAY (1 << 3)
+#define REGC_WORD_WIDTH(x) ((x & 0x3) << 4)
+
+/* Control register D */
+#define CTRL_REG_D (3 << 11)
+
+#define REGD_MASTER (1 << 0)
+#define REGD_FDCLK (1 << 1)
+#define REGD_DSP_MODE (1 << 2)
+#define REGD_MIX_MODE (1 << 3)
+#define REGD_MFS (1 << 9)
+
+/* Control register E */
+#define CTRL_REG_E (4 << 11)
+
+#define REGE_DAC_MUTE (1 << 0)
+#define REGE_ADC_MUTE (1 << 1)
+#define REGE_ADC_GAIN(x) ((x & 0x7) << 2)
+#define REGE_ADC_PEAKEN (1 << 5)
+
+/* Control register F */
+#define CTRL_REG_F (5 << 11)
+#define REGF_DAC_VOL(x) (x & 0x3F)
+
+/* Control register G */
+#define CTRL_REG_G (6 << 11)
#endif
+
+#endif
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