commit: http://blackfin.uclinux.org/git/?p=linux-kernel;a=commitdiff;h=9e8145c3e4b1915f252e3fbd98a4bc8d48b46f26 branch: http://blackfin.uclinux.org/git/?p=linux-kernel;a=shortlog;h=refs/heads/trunk
In blackfin SMP architecture, no cache coherence among cores is supppored by hardware. Data protected by spin lock or atomic operation are kept consistent by invalidating entired local cache in spin lock APIs and smp memory barrier APIs on the other cores. Non atomic operations in current Blackfin SMP kernel run smp memory barrier. This patch add smp memory barrier to some atomic operations that are defined in Documents/memory-barriers.txt . Signed-off-by: Sonic Zhang <[email protected]> Signed-off-by: Bob Liu <[email protected]> --- arch/blackfin/include/asm/cmpxchg.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/blackfin/include/asm/cmpxchg.h b/arch/blackfin/include/asm/cmpxchg.h index ba2484f..831e6d5 100644 --- a/arch/blackfin/include/asm/cmpxchg.h +++ b/arch/blackfin/include/asm/cmpxchg.h @@ -63,6 +63,8 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, break; } + smp_mb(); + return tmp; } #define cmpxchg(ptr, o, n) \
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