commit: http://blackfin.uclinux.org/git/?p=linux-kernel;a=commitdiff;h=7e6c4eb3012d8a423b0c7d6a786eec3611637ba6 branch: http://blackfin.uclinux.org/git/?p=linux-kernel;a=shortlog;h=refs/heads/trunk
Signed-off-by: Steven Miao <[email protected]> Signed-off-by: Bob Liu <[email protected]> --- arch/blackfin/include/asm/gptimers.h | 115 ++++++++++++++++++ arch/blackfin/kernel/gptimers.c | 17 +++ .../mach-bf609/include/mach/defBF60x_base.h | 122 ++++++++++--------- 3 files changed, 196 insertions(+), 58 deletions(-) diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h index 38bddcb..d5267ee 100644 --- a/arch/blackfin/include/asm/gptimers.h +++ b/arch/blackfin/include/asm/gptimers.h @@ -44,6 +44,13 @@ # define TIMER_GROUP2 1 #endif /* + * BF609: 8 timers: + */ +#if defined(CONFIG_BF60x) +# define MAX_BLACKFIN_GPTIMERS 8 +# define TIMER0_GROUP_REG TIMER_RUN +#endif +/* * All others: 3 timers: */ #define TIMER_GROUP1 0 @@ -104,6 +111,82 @@ # define FS2_TIMER_BIT TIMER1bit #endif +#ifdef CONFIG_BF60x +/* + * Timer Configuration Register Bits + */ +#define TIMER_EMU_RUN 0x8000 +#define TIMER_BPER_EN 0x4000 +#define TIMER_BWID_EN 0x2000 +#define TIMER_BDLY_EN 0x1000 +#define TIMER_OUT_DIS 0x0800 +#define TIMER_TIN_SEL 0x0400 +#define TIMER_CLK_SEL 0x0300 +#define TIMER_CLK_SCLK 0x0000 +#define TIMER_CLK_ALT_CLK0 0x0100 +#define TIMER_CLK_ALT_CLK1 0x0300 +#define TIMER_PULSE_HI 0x0080 +#define TIMER_SLAVE_TRIG 0x0040 +#define TIMER_IRQ_MODE 0x0030 +#define TIMER_IRQ_ACT_EDGE 0x0000 +#define TIMER_IRQ_DLY 0x0010 +#define TIMER_IRQ_WID_DLY 0x0020 +#define TIMER_IRQ_PER 0x0030 + +#define TIMER_ERR 0xC000 +#define TIMER_ERR_OVFL 0x4000 +#define TIMER_ERR_PROG_PER 0x8000 +#define TIMER_ERR_PROG_PW 0xC000 +#define TIMER_MODE 0x000f +#define TIMER_MODE_WDOG_P 0x0008 +#define TIMER_MODE_WDOG_W 0x0009 +#define TIMER_MODE_PWM_CONT 0x000c +#define TIMER_MODE_PWM 0x000d +#define TIMER_MODE_WDTH 0x000a +#define TIMER_MODE_WDTH_D 0x000b +#define TIMER_MODE_EXT_CLK 0x000e +#define TIMER_MODE_PININT 0x000f + +/* + * Timer Status Register Bits + */ +#define TIMER_STATUS_TIMIL0 0x0001 +#define TIMER_STATUS_TIMIL1 0x0002 +#define TIMER_STATUS_TIMIL2 0x0004 +#define TIMER_STATUS_TIMIL3 0x00000008 +#define TIMER_STATUS_TIMIL4 0x00010000 +#define TIMER_STATUS_TIMIL5 0x00020000 +#define TIMER_STATUS_TIMIL6 0x00040000 +#define TIMER_STATUS_TIMIL7 0x00080000 + +#define TIMER_STATUS_TOVF0 0x0003 /* timer 0 overflow error */ +#define TIMER_STATUS_TOVF1 0x000c +#define TIMER_STATUS_TOVF2 0x0030 +#define TIMER_STATUS_TOVF3 0x00c0 +#define TIMER_STATUS_TOVF4 0x0300 +#define TIMER_STATUS_TOVF5 0x0c00 +#define TIMER_STATUS_TOVF6 0x3000 +#define TIMER_STATUS_TOVF7 0xc000 + +/* + * Timer Slave Enable Status : write 1 to clear + */ +#define TIMER_STATUS_TRUN0 0x1000 +#define TIMER_STATUS_TRUN1 0x2000 +#define TIMER_STATUS_TRUN2 0x4000 +#define TIMER_STATUS_TRUN3 0x00008000 +#define TIMER_STATUS_TRUN4 0x10000000 +#define TIMER_STATUS_TRUN5 0x20000000 +#define TIMER_STATUS_TRUN6 0x40000000 +#define TIMER_STATUS_TRUN7 0x80000000 +#define TIMER_STATUS_TRUN 0xF000F000 +#define TIMER_STATUS_TRUN8 0x1000 +#define TIMER_STATUS_TRUN9 0x2000 +#define TIMER_STATUS_TRUN10 0x4000 +#define TIMER_STATUS_TRUN11 0x8000 + +#else + /* * Timer Configuration Register Bits */ @@ -170,12 +253,18 @@ #define TIMER_STATUS_TRUN10 0x4000 #define TIMER_STATUS_TRUN11 0x8000 +#endif + /* The actual gptimer API */ void set_gptimer_pwidth(unsigned int timer_id, uint32_t width); uint32_t get_gptimer_pwidth(unsigned int timer_id); void set_gptimer_period(unsigned int timer_id, uint32_t period); uint32_t get_gptimer_period(unsigned int timer_id); +#ifdef CONFIG_BF60x +void set_gptimer_delay(unsigned int timer_id, uint32_t delay); +uint32_t get_gptimer_delay(unsigned int timer_id); +#endif uint32_t get_gptimer_count(unsigned int timer_id); int get_gptimer_intr(unsigned int timer_id); void clear_gptimer_intr(unsigned int timer_id); @@ -217,16 +306,42 @@ struct bfin_gptimer_regs { u32 counter; u32 period; u32 width; +#ifdef CONFIG_BF60x + u32 delay; +#endif }; /* * bfin group timer registers layout */ +#ifndef CONFIG_BF60x struct bfin_gptimer_group_regs { __BFP(enable); __BFP(disable); u32 status; }; +#else +struct bfin_gptimer_group_regs { + __BFP(revid); + __BFP(run); + __BFP(enable); + __BFP(disable); + __BFP(stop_cfg); + __BFP(stop_cfg_set); + __BFP(stop_cfg_clr); + __BFP(data_imsk); + __BFP(stat_imsk); + __BFP(tr_msk); + __BFP(tr_ie); + __BFP(data_ilat); + __BFP(stat_ilat); + __BFP(status); + __BFP(bcast_per); + __BFP(bcast_wid); + __BFP(bcast_dly); + +}; +#endif #undef __BFP diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c index 06459f4..e800d4d 100644 --- a/arch/blackfin/kernel/gptimers.c +++ b/arch/blackfin/kernel/gptimers.c @@ -158,6 +158,23 @@ uint32_t get_gptimer_count(unsigned int timer_id) } EXPORT_SYMBOL(get_gptimer_count); +#ifdef CONFIG_BF60x +void set_gptimer_delay(unsigned int timer_id, uint32_t delay) +{ + tassert(timer_id < MAX_BLACKFIN_GPTIMERS); + bfin_write(&timer_regs[timer_id]->delay, delay); + SSYNC(); +} +EXPORT_SYMBOL(set_gptimer_delay); + +uint32_t get_gptimer_delay(unsigned int timer_id) +{ + tassert(timer_id < MAX_BLACKFIN_GPTIMERS); + return bfin_read(&timer_regs[timer_id]->delay); +} +EXPORT_SYMBOL(get_gptimer_delay); +#endif + uint32_t get_gptimer_status(unsigned int group) { tassert(group < BFIN_TIMER_NUM_GROUP); diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h index e7bda4f..412e518 100644 --- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h +++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h @@ -440,68 +440,74 @@ /* ========================= TIMER Registers ========================= */ - -/* ========================= - TIMER0 - ========================= */ -#define TIMER_REVID 0xFFC01400 /* TIMER0 Timer IP Version ID */ -#define TIMER_RUN 0xFFC01404 /* TIMER0 Timer Run Register */ -#define TIMER_RUN_SET 0xFFC01408 /* TIMER0 Run Register Alias to Set */ -#define TIMER_RUN_CLR 0xFFC0140C /* TIMER0 Run Register Alias to Clear */ -#define TIMER_STOP_CFG 0xFFC01410 /* TIMER0 Stop Config Register */ -#define TIMER_STOP_CFG_SET 0xFFC01414 /* TIMER0 Stop Config Alias to Set */ -#define TIMER_STOP_CFG_CLR 0xFFC01418 /* TIMER0 Stop Config Alias to Clear */ -#define TIMER_DATA_IMSK 0xFFC0141C /* TIMER0 Data Interrupt Mask register */ -#define TIMER_STAT_IMSK 0xFFC01420 /* TIMER0 Status Interrupt Mask register */ -#define TIMER_TRG_MSK 0xFFC01424 /* TIMER0 Output Trigger Mask register */ -#define TIMER_TRG_IE 0xFFC01428 /* TIMER0 Slave Trigger Enable register */ -#define TIMER_DATA_ILAT 0xFFC0142C /* TIMER0 Data Interrupt Register */ -#define TIMER_STAT_ILAT 0xFFC01430 /* TIMER0 Status (Error) Interrupt Register */ -#define TIMER_ERR_TYPE 0xFFC01434 /* TIMER0 Register Indicating Type of Error */ -#define TIMER_BCAST_PER 0xFFC01438 /* TIMER0 Broadcast Period */ -#define TIMER_BCAST_WID 0xFFC0143C /* TIMER0 Broadcast Width */ -#define TIMER_BCAST_DLY 0xFFC01440 /* TIMER0 Broadcast Delay */ -#define TIMER_TMR0_CFG 0xFFC01460 /* TIMER0 Per Timer Config Register */ -#define TIMER_TMR1_CFG 0xFFC01480 /* TIMER0 Per Timer Config Register */ -#define TIMER_TMR2_CFG 0xFFC014A0 /* TIMER0 Per Timer Config Register */ -#define TIMER_TMR3_CFG 0xFFC014C0 /* TIMER0 Per Timer Config Register */ -#define TIMER_TMR4_CFG 0xFFC014E0 /* TIMER0 Per Timer Config Register */ -#define TIMER_TMR5_CFG 0xFFC01500 /* TIMER0 Per Timer Config Register */ -#define TIMER_TMR6_CFG 0xFFC01520 /* TIMER0 Per Timer Config Register */ -#define TIMER_TMR7_CFG 0xFFC01540 /* TIMER0 Per Timer Config Register */ -#define TIMER_TMR0_CNT 0xFFC01464 /* TIMER0 Per Timer Counter Register */ -#define TIMER_TMR1_CNT 0xFFC01484 /* TIMER0 Per Timer Counter Register */ -#define TIMER_TMR2_CNT 0xFFC014A4 /* TIMER0 Per Timer Counter Register */ -#define TIMER_TMR3_CNT 0xFFC014C4 /* TIMER0 Per Timer Counter Register */ -#define TIMER_TMR4_CNT 0xFFC014E4 /* TIMER0 Per Timer Counter Register */ -#define TIMER_TMR5_CNT 0xFFC01504 /* TIMER0 Per Timer Counter Register */ -#define TIMER_TMR6_CNT 0xFFC01524 /* TIMER0 Per Timer Counter Register */ -#define TIMER_TMR7_CNT 0xFFC01544 /* TIMER0 Per Timer Counter Register */ -#define TIMER_TMR0_PER 0xFFC01468 /* TIMER0 Per Timer Period Register */ -#define TIMER_TMR1_PER 0xFFC01488 /* TIMER0 Per Timer Period Register */ -#define TIMER_TMR2_PER 0xFFC014A8 /* TIMER0 Per Timer Period Register */ -#define TIMER_TMR3_PER 0xFFC014C8 /* TIMER0 Per Timer Period Register */ -#define TIMER_TMR4_PER 0xFFC014E8 /* TIMER0 Per Timer Period Register */ -#define TIMER_TMR5_PER 0xFFC01508 /* TIMER0 Per Timer Period Register */ -#define TIMER_TMR6_PER 0xFFC01528 /* TIMER0 Per Timer Period Register */ -#define TIMER_TMR7_PER 0xFFC01548 /* TIMER0 Per Timer Period Register */ -#define TIMER_TMR0_WID 0xFFC0146C /* TIMER0 Per Timer Width Register */ -#define TIMER_TMR1_WID 0xFFC0148C /* TIMER0 Per Timer Width Register */ -#define TIMER_TMR2_WID 0xFFC014AC /* TIMER0 Per Timer Width Register */ -#define TIMER_TMR3_WID 0xFFC014CC /* TIMER0 Per Timer Width Register */ -#define TIMER_TMR4_WID 0xFFC014EC /* TIMER0 Per Timer Width Register */ -#define TIMER_TMR5_WID 0xFFC0150C /* TIMER0 Per Timer Width Register */ -#define TIMER_TMR6_WID 0xFFC0152C /* TIMER0 Per Timer Width Register */ -#define TIMER_TMR7_WID 0xFFC0154C /* TIMER0 Per Timer Width Register */ -#define TIMER_TMR0_DLY 0xFFC01470 /* TIMER0 Per Timer Delay Register */ -#define TIMER_TMR1_DLY 0xFFC01490 /* TIMER0 Per Timer Delay Register */ -#define TIMER_TMR2_DLY 0xFFC014B0 /* TIMER0 Per Timer Delay Register */ -#define TIMER_TMR3_DLY 0xFFC014D0 /* TIMER0 Per Timer Delay Register */ -#define TIMER_TMR4_DLY 0xFFC014F0 /* TIMER0 Per Timer Delay Register */ -#define TIMER_TMR5_DLY 0xFFC01510 /* TIMER0 Per Timer Delay Register */ -#define TIMER_TMR6_DLY 0xFFC01530 /* TIMER0 Per Timer Delay Register */ -#define TIMER_TMR7_DLY 0xFFC01550 /* TIMER0 Per Timer Delay Register */ - +#define TIMER_REVID 0xFFC01400 /* GPTIMER Timer IP Version ID */ +#define TIMER_RUN 0xFFC01404 /* GPTIMER Timer Run Register */ +#define TIMER_RUN_SET 0xFFC01408 /* GPTIMER Run Register Alias to Set */ +#define TIMER_RUN_CLR 0xFFC0140C /* GPTIMER Run Register Alias to Clear */ +#define TIMER_STOP_CFG 0xFFC01410 /* GPTIMER Stop Config Register */ +#define TIMER_STOP_CFG_SET 0xFFC01414 /* GPTIMER Stop Config Alias to Set */ +#define TIMER_STOP_CFG_CLR 0xFFC01418 /* GPTIMER Stop Config Alias to Clear */ +#define TIMER_DATA_IMSK 0xFFC0141C /* GPTIMER Data Interrupt Mask register */ +#define TIMER_STAT_IMSK 0xFFC01420 /* GPTIMER Status Interrupt Mask register */ +#define TIMER_TRG_MSK 0xFFC01424 /* GPTIMER Output Trigger Mask register */ +#define TIMER_TRG_IE 0xFFC01428 /* GPTIMER Slave Trigger Enable register */ +#define TIMER_DATA_ILAT 0xFFC0142C /* GPTIMER Data Interrupt Register */ +#define TIMER_STAT_ILAT 0xFFC01430 /* GPTIMER Status (Error) Interrupt Register */ +#define TIMER_ERR_TYPE 0xFFC01434 /* GPTIMER Register Indicating Type of Error */ +#define TIMER_BCAST_PER 0xFFC01438 /* GPTIMER Broadcast Period */ +#define TIMER_BCAST_WID 0xFFC0143C /* GPTIMER Broadcast Width */ +#define TIMER_BCAST_DLY 0xFFC01440 /* GPTIMER Broadcast Delay */ + +/* ========================= + TIMER0~7 + ========================= */ +#define TIMER0_CONFIG 0xFFC01460 /* TIMER0 Per Timer Config Register */ +#define TIMER0_COUNTER 0xFFC01464 /* TIMER0 Per Timer Counter Register */ +#define TIMER0_PERIOD 0xFFC01468 /* TIMER0 Per Timer Period Register */ +#define TIMER0_WIDTH 0xFFC0146C /* TIMER0 Per Timer Width Register */ +#define TIMER0_DELAY 0xFFC01470 /* TIMER0 Per Timer Delay Register */ + +#define TIMER1_CONFIG 0xFFC01480 /* TIMER1 Per Timer Config Register */ +#define TIMER1_COUNTER 0xFFC01484 /* TIMER1 Per Timer Counter Register */ +#define TIMER1_PERIOD 0xFFC01488 /* TIMER1 Per Timer Period Register */ +#define TIMER1_WIDTH 0xFFC0148C /* TIMER1 Per Timer Width Register */ +#define TIMER1_DELAY 0xFFC01490 /* TIMER1 Per Timer Delay Register */ + +#define TIMER2_CONFIG 0xFFC014A0 /* TIMER2 Per Timer Config Register */ +#define TIMER2_COUNTER 0xFFC014A4 /* TIMER2 Per Timer Counter Register */ +#define TIMER2_PERIOD 0xFFC014A8 /* TIMER2 Per Timer Period Register */ +#define TIMER2_WIDTH 0xFFC014AC /* TIMER2 Per Timer Width Register */ +#define TIMER2_DELAY 0xFFC014B0 /* TIMER2 Per Timer Delay Register */ + +#define TIMER3_CONFIG 0xFFC014C0 /* TIMER3 Per Timer Config Register */ +#define TIMER3_COUNTER 0xFFC014C4 /* TIMER3 Per Timer Counter Register */ +#define TIMER3_PERIOD 0xFFC014C8 /* TIMER3 Per Timer Period Register */ +#define TIMER3_WIDTH 0xFFC014CC /* TIMER3 Per Timer Width Register */ +#define TIMER3_DELAY 0xFFC014D0 /* TIMER3 Per Timer Delay Register */ + +#define TIMER4_CONFIG 0xFFC014E0 /* TIMER4 Per Timer Config Register */ +#define TIMER4_COUNTER 0xFFC014E4 /* TIMER4 Per Timer Counter Register */ +#define TIMER4_PERIOD 0xFFC014E8 /* TIMER4 Per Timer Period Register */ +#define TIMER4_WIDTH 0xFFC014EC /* TIMER4 Per Timer Width Register */ +#define TIMER4_DELAY 0xFFC014F0 /* TIMER4 Per Timer Delay Register */ + +#define TIMER5_CONFIG 0xFFC01500 /* TIMER5 Per Timer Config Register */ +#define TIMER5_COUNTER 0xFFC01504 /* TIMER5 Per Timer Counter Register */ +#define TIMER5_PERIOD 0xFFC01508 /* TIMER5 Per Timer Period Register */ +#define TIMER5_WIDTH 0xFFC0150C /* TIMER5 Per Timer Width Register */ +#define TIMER5_DELAY 0xFFC01510 /* TIMER5 Per Timer Delay Register */ + +#define TIMER6_CONFIG 0xFFC01520 /* TIMER6 Per Timer Config Register */ +#define TIMER6_COUNTER 0xFFC01524 /* TIMER6 Per Timer Counter Register */ +#define TIMER6_PERIOD 0xFFC01528 /* TIMER6 Per Timer Period Register */ +#define TIMER6_WIDTH 0xFFC0152C /* TIMER6 Per Timer Width Register */ +#define TIMER6_DELAY 0xFFC01530 /* TIMER6 Per Timer Delay Register */ + +#define TIMER7_CONFIG 0xFFC01540 /* TIMER7 Per Timer Config Register */ +#define TIMER7_COUNTER 0xFFC01544 /* TIMER7 Per Timer Counter Register */ +#define TIMER7_PERIOD 0xFFC01548 /* TIMER7 Per Timer Period Register */ +#define TIMER7_WIDTH 0xFFC0154C /* TIMER7 Per Timer Width Register */ +#define TIMER7_DELAY 0xFFC01550 /* TIMER7 Per Timer Delay Register */ /* ========================= TWI Registers
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