commit: http://blackfin.uclinux.org/git/?p=linux-kernel;a=commitdiff;h=69f3a2008395c9ff62767a2261a0433397adbee2 branch: http://blackfin.uclinux.org/git/?p=linux-kernel;a=shortlog;h=refs/heads/trunk
LCR is part of CTL MMR on bf6xx. Mask LCR bits before set new value. Signed-off-by: Sonic Zhang <[email protected]> Signed-off-by: Bob Liu <[email protected]> --- arch/blackfin/include/asm/bfin_serial.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h index 442577d..c3bf9bd 100644 --- a/arch/blackfin/include/asm/bfin_serial.h +++ b/arch/blackfin/include/asm/bfin_serial.h @@ -76,6 +76,7 @@ struct bfin_serial_port { #define FPE 0x20000 /* Force Parity Error On Transmit */ #define FFE 0x40000 /* Force Framing Error On Transmit */ #define SB 0x80000 /* Set Break */ +#define LCR_MASK (SB | STP | EPS | PEN | STBH | STB | WLS_MASK) #define FCPOL 0x400000 /* Flow Control Pin Polarity */ #define RPOLC 0x800000 /* IrDA RX Polarity Change */ #define TPOLC 0x1000000 /* IrDA TX Polarity Change */ @@ -117,6 +118,7 @@ struct bfin_serial_port { #define STP 0x20 /* Stick Parity */ #define SB 0x40 /* Set Break */ #define DLAB 0x80 /* Divisor Latch Access */ +#define LCR_MASK (SB | STP | EPS | PEN | STB | DLAB | WLS_MASK) /* UART_LSR Masks */ #define DR 0x01 /* Data Ready */
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