commit: http://blackfin.uclinux.org/git/?p=linux-kernel;a=commitdiff;h=f75cb3633c3ace9f2cbd9426c14dac13c101b3cb branch: http://blackfin.uclinux.org/git/?p=linux-kernel;a=shortlog;h=refs/heads/trunk
hibernate pm callback bootrom syscontrol support wakeup sources configuration Signed-off-by: Steven Miao <[email protected]> Signed-off-by: Bob Liu <[email protected]> --- arch/blackfin/mach-bf609/pm.c | 280 +++++++++++++++++++++++++++++------------ 1 files changed, 199 insertions(+), 81 deletions(-) diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c index 576721b..81c9633 100644 --- a/arch/blackfin/mach-bf609/pm.c +++ b/arch/blackfin/mach-bf609/pm.c @@ -10,13 +10,118 @@ #include <linux/io.h> #include <linux/interrupt.h> #include <linux/gpio.h> +#include <linux/irq.h> #include <linux/delay.h> #include <asm/dpmc.h> #include <asm/pm.h> #include <mach/pm.h> +#include <asm/blackfin.h> + +/***********************************************************/ +/* */ +/* Wakeup Actions for DPM_RESTORE */ +/* */ +/***********************************************************/ +#define BITP_ROM_WUA_CHKHDR 24 +#define BITP_ROM_WUA_DDRLOCK 7 +#define BITP_ROM_WUA_DDRDLLEN 6 +#define BITP_ROM_WUA_DDR 5 +#define BITP_ROM_WUA_CGU 4 +#define BITP_ROM_WUA_MEMBOOT 2 +#define BITP_ROM_WUA_EN 1 + +#define BITM_ROM_WUA_CHKHDR (0xFF000000) +#define ENUM_ROM_WUA_CHKHDR_AD 0xAD000000 + +#define BITM_ROM_WUA_DDRLOCK (0x00000080) +#define BITM_ROM_WUA_DDRDLLEN (0x00000040) +#define BITM_ROM_WUA_DDR (0x00000020) +#define BITM_ROM_WUA_CGU (0x00000010) +#define BITM_ROM_WUA_MEMBOOT (0x00000002) +#define BITM_ROM_WUA_EN (0x00000001) + +/***********************************************************/ +/* */ +/* Syscontrol */ +/* */ +/***********************************************************/ +#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN 28 /* unlocks CGU_CTL register */ +#define BITP_ROM_SYSCTRL_WUA_OVERRIDE 24 +#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN 20 /* Saves the DDR DLL and PADS registers to the DPM registers */ +#define BITP_ROM_SYSCTRL_WUA_DDR 19 /* Saves the DDR registers to the DPM registers */ +#define BITP_ROM_SYSCTRL_WUA_CGU 18 /* Saves the CGU registers into DPM registers */ +#define BITP_ROM_SYSCTRL_WUA_DPMWRITE 17 /* Saves the Syscontrol structure structure contents into DPM registers */ +#define BITP_ROM_SYSCTRL_WUA_EN 16 /* reads current PLL and DDR configuration into structure */ +#define BITP_ROM_SYSCTRL_DDR_WRITE 13 /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */ +#define BITP_ROM_SYSCTRL_DDR_READ 12 /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */ +#define BITP_ROM_SYSCTRL_CGU_AUTODIS 11 /* Disables auto handling of UPDT and ALGN fields */ +#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL 7 /* access CGU_CLKOUTSEL register */ +#define BITP_ROM_SYSCTRL_CGU_DIV 6 /* access CGU_DIV register */ +#define BITP_ROM_SYSCTRL_CGU_STAT 5 /* access CGU_STAT register */ +#define BITP_ROM_SYSCTRL_CGU_CTL 4 /* access CGU_CTL register */ +#define BITP_ROM_SYSCTRL_CGU_RTNSTAT 2 /* Update structure STAT field upon error */ +#define BITP_ROM_SYSCTRL_WRITE 1 /* write registers */ +#define BITP_ROM_SYSCTRL_READ 0 /* read registers */ + +#define BITM_ROM_SYSCTRL_CGU_READ (0x00000001) /* Read CGU registers */ +#define BITM_ROM_SYSCTRL_CGU_WRITE (0x00000002) /* Write registers */ +#define BITM_ROM_SYSCTRL_CGU_RTNSTAT (0x00000004) /* Update structure STAT field upon error or after a write operation */ +#define BITM_ROM_SYSCTRL_CGU_CTL (0x00000010) /* Access CGU_CTL register */ +#define BITM_ROM_SYSCTRL_CGU_STAT (0x00000020) /* Access CGU_STAT register */ +#define BITM_ROM_SYSCTRL_CGU_DIV (0x00000040) /* Access CGU_DIV register */ +#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL (0x00000080) /* Access CGU_CLKOUTSEL register */ +#define BITM_ROM_SYSCTRL_CGU_AUTODIS (0x00000800) /* Disables auto handling of UPDT and ALGN fields */ +#define BITM_ROM_SYSCTRL_DDR_READ (0x00001000) /* Reads the contents of the DDR registers and stores them into the structure */ +#define BITM_ROM_SYSCTRL_DDR_WRITE (0x00002000) /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */ +#define BITM_ROM_SYSCTRL_WUA_EN (0x00010000) /* Wakeup entry or exit opertation enable */ +#define BITM_ROM_SYSCTRL_WUA_DPMWRITE (0x00020000) /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */ +#define BITM_ROM_SYSCTRL_WUA_CGU (0x00040000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */ +#define BITM_ROM_SYSCTRL_WUA_DDR (0x00080000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */ +#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN (0x00100000) /* Enables saving/restoring of the DDR DLLCTL register */ +#define BITM_ROM_SYSCTRL_WUA_OVERRIDE (0x01000000) +#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN (0x10000000) /* Unlocks the CGU_CTL register */ + + +/* Structures for the syscontrol() function */ +struct STRUCT_ROM_SYSCTRL { + uint32_t ulCGU_CTL; + uint32_t ulCGU_STAT; + uint32_t ulCGU_DIV; + uint32_t ulCGU_CLKOUTSEL; + uint32_t ulWUA_Flags; + uint32_t ulWUA_BootAddr; + uint32_t ulWUA_User; + uint32_t ulDDR_CTL; + uint32_t ulDDR_CFG; + uint32_t ulDDR_TR0; + uint32_t ulDDR_TR1; + uint32_t ulDDR_TR2; + uint32_t ulDDR_MR; + uint32_t ulDDR_EMR1; + uint32_t ulDDR_EMR2; + uint32_t ulDDR_PADCTL; + uint32_t ulDDR_DLLCTL; + uint32_t ulReserved; +}; + +struct bfin_pm_data { + uint32_t magic; + uint32_t resume_addr; + uint32_t sp; +}; + +struct bfin_pm_data bf609_pm_data; + +struct STRUCT_ROM_SYSCTRL configvalues; +uint32_t dactionflags; +#define FUNC_ROM_SYSCONTROL 0xC8000080 +__attribute__((l1_data)) +static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL; + +__attribute__((l1_text)) void bfin_cpu_suspend(void) { __asm__ __volatile__( \ @@ -26,65 +131,45 @@ void bfin_cpu_suspend(void) ); } -void pm_dump_reg(void) +uint32_t pm_reg[512]; +uint32_t pm_reg_val[512]; +uint32_t pm_reg_num = 0; + +void pm_save_reg(uint32_t addr, uint32_t value) { - uint32_t reg; - reg = bfin_read32(SEC_SCTL1); - printk("SEC_SCTL1 %08x %08x\n", SEC_SCTL1, reg); + pm_reg[pm_reg_num] = addr; + pm_reg_val[pm_reg_num] = value; + pm_reg_num++; } -void bfin_deepsleep(unsigned long mask) +void pm_dump_reg(void) { - uint32_t dpm0_ctl; - - bfin_write32(DPM0_WAKE_EN, mask); + int i; - dpm0_ctl = bfin_read32(DPM0_CTL); - dpm0_ctl = 0x00000008; - bfin_write32(DPM0_CTL, dpm0_ctl); - bfin_write32(DPM0_WAKE_EN, mask); - bfin_write32(DPM0_WAKE_POL, 0); - SSYNC(); - pm_dump_reg(); -#if 1 - while (1) { - mdelay(500); - printk("idle\n"); + for (i = 0; i < pm_reg_num; i++) { + printk("reg %08x: %08x\n", pm_reg[i], pm_reg_val[i]); } -#endif - bfin_cpu_suspend(); - } -void bfin_hibernate(unsigned long mask) +__attribute__((l1_text)) +void bfin_deepsleep(unsigned long mask) { uint32_t dpm0_ctl; - int i = 100000000; - - bfin_write32(DPM0_WAKE_EN, mask); - bfin_write32(DPM0_WAKE_POL, 0); - bfin_write32(DPM0_RESTORE0, 0xFFAABBCC); - bfin_write32(DPM0_PGCNTR, 0x0000FFFF); - bfin_write32(DPM0_HIB_DIS, 0xFFFF); - SSYNC(); - - printk("hibernate: restore %x pgcnt %x\n", bfin_read32(DPM0_RESTORE0), bfin_read32(DPM0_PGCNTR)); + bfin_write32(DPM0_WAKE_EN, 0x10); + bfin_write32(DPM0_WAKE_POL, 0x10); dpm0_ctl = bfin_read32(DPM0_CTL); - dpm0_ctl = 0x00000010; + dpm0_ctl = 0x00000008; bfin_write32(DPM0_CTL, dpm0_ctl); SSYNC(); - -#if 1 - while (1) { - mdelay(500); - printk("idle\n"); - } -#endif - - bf609_hibernate(); + __asm__ __volatile__( \ + ".align 8;" \ + "idle;" \ + : : \ + ); } +__attribute__((l1_text)) void bf609_ddr_sr(void) { uint32_t reg; @@ -97,18 +182,11 @@ void bf609_ddr_sr(void) continue; } +__attribute__((l1_text)) void bf609_ddr_sr_exit(void) { uint32_t reg; - uint32_t dll_ctl; - uint32_t dlldatacycle; - - reg = bfin_read_DDR0_CTL(); - reg |= 0x8; - bfin_write_DDR0_CTL(reg); - while (!(bfin_read_DDR0_STAT() & 0x4)) - continue; - while (!(bfin_read_DDR0_STAT() & 0x8)) + while (!(bfin_read_DDR0_STAT() & 0x1)) continue; reg = bfin_read_DDR0_CTL(); @@ -117,28 +195,58 @@ void bf609_ddr_sr_exit(void) while ((bfin_read_DDR0_STAT() & 0x8)) continue; +} - dlldatacycle = (bfin_read_DDR0_STAT() & 0x00f00000) >> 20; - dll_ctl = bfin_read_DDR0_DLLCTL(); - dll_ctl &= 0x0ff; - bfin_write_DDR0_DLLCTL(dll_ctl | (dlldatacycle << 8)); +__attribute__((l1_text)) +void bfin_hibernate_syscontrol(void) +{ + configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN + | BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN); - while (!(bfin_read_DDR0_STAT() & 0x2000)) - continue; + dactionflags = (BITM_ROM_SYSCTRL_WUA_EN + | BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU + | BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN); + + bfrom_SysControl(dactionflags, &configvalues, NULL); + + bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4); +} + +#ifndef CONFIG_BF60x +# define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) +#else +# define SIC_SYSIRQ(irq) ((irq) - IVG15) +#endif +void bfin_sec_resume(void); + +void bfin_hibernate(unsigned long mask) +{ + bfin_write32(DPM0_WAKE_EN, 0x10); + bfin_write32(DPM0_WAKE_POL, 0x10); + bfin_write32(DPM0_PGCNTR, 0x0000FFFF); + bfin_write32(DPM0_HIB_DIS, 0xFFFF); + printk(KERN_DEBUG "hibernate: restore %x pgcnt %x\n", bfin_read32(DPM0_RESTORE0), bfin_read32(DPM0_PGCNTR)); + + bf609_hibernate(); + bfin_sec_resume(); } void bf609_cpu_pm_enter(suspend_state_t state) { int error; error = irq_set_irq_wake(255, 1); + if(error < 0) + printk(KERN_DEBUG "Unable to get irq wake\n"); + error = irq_set_irq_wake(231, 1); if (error < 0) - printk("Unable to get irq wake\n"); + printk(KERN_DEBUG "Unable to get irq wake\n"); if (state == PM_SUSPEND_STANDBY) bfin_deepsleep(0xffff); - else + else { bfin_hibernate(0xffff); + } } int bf609_cpu_pm_prepare(void) @@ -159,13 +267,18 @@ static struct bfin_cpu_pm_fns bf609_cpu_pm = { static irqreturn_t test_isr(int irq, void *dev_id) { - printk("gpio irq %d\n", irq); + printk(KERN_DEBUG "gpio irq %d\n", irq); return IRQ_HANDLED; } -static irqreturn_t dummy_isr(int irq, void *dev_id) +static irqreturn_t dpm0_isr(int irq, void *dev_id) { - printk("enter %s\n", __func__); + uint32_t wake_stat; + + wake_stat = bfin_read32(DPM0_WAKE_STAT); + printk(KERN_DEBUG "enter %s wake stat %08x\n", __func__, wake_stat); + + bfin_write32(DPM0_WAKE_STAT, wake_stat); return IRQ_HANDLED; } @@ -175,38 +288,43 @@ static int __init bf609_init_pm(void) int error; error = gpio_request(GPIO_PG4, "gpiopg4"); if (error < 0) { - printk("failed to request GPIO %d, error %d\n", - GPIO_PG4, error); - } - - error = gpio_direction_input(GPIO_PG4); - if (error < 0) { - printk("failed to configure" - " direction for GPIO %d, error %d\n", + printk(KERN_DEBUG "failed to request GPIO %d, error %d\n", GPIO_PG4, error); } irq = gpio_to_irq(GPIO_PG4); if (irq < 0) { error = irq; - printk("Unable to get irq number for GPIO %d, error %d\n", + printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n", GPIO_PG4, error); } - printk("%s gpio %d irq %d\n", __func__, GPIO_PG4, irq); + printk(KERN_DEBUG "%s gpio %d irq %d\n", __func__, GPIO_PG4, irq); error = request_irq(irq, test_isr, IRQF_TRIGGER_FALLING | IRQF_NO_SUSPEND, "gpiopg4", NULL); - if (error < 0) - printk("Unable to get irq\n"); + if(error < 0) + printk(KERN_DEBUG "Unable to get irq\n"); - error = request_irq(IRQ_CGU_EVT, dummy_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL); - if (error < 0) - printk("Unable to get irq\n"); +#if 1 + irq = gpio_to_irq(GPIO_PE12); + if (irq < 0) { + error = irq; + printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n", + GPIO_PE12, error); + } - error = request_irq(IRQ_DPM, dummy_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL); - if (error < 0) - printk("Unable to get irq\n"); + error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL); + if(error < 0) + printk(KERN_DEBUG "Unable to get irq\n"); +#endif + error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL); + if(error < 0) + printk(KERN_DEBUG "Unable to get irq\n"); + + error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL); + if (error < 0) + printk(KERN_DEBUG "Unable to get irq\n"); bfin_cpu_pm = &bf609_cpu_pm; return 0;
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