Michel Lanners wrote:
> >> static inline int pci_enable_device(struct pci_device *dev)
> >> {
> >> return pci_enable_device_features(USE_IO|USE_MM);
> >> }
> (snip)
> > And what about other features ?
> > I mean:
> > - Bus Master
> > - Memory Write and Invalidate
> > - Parity Error response
>
> This should probably be handled in arch-dependant code. So make a
> pci_enable_device() per arch. The point beeing that only this code has a
> chance to know some of the details of the PCI implementation on this
> platform/arch. Bus master and MemWI don't hurt, but I guess enabling
> parity can halt the bus. So you want to be careful...
Take a look at the drivers/net/acenic.c driver. It enables/disables
Memory Write and Invalidate one way or another, but the decision is not
arch-specific. It gets worse: it writes cache line size to PCI_COMMAND
as well.
-- Jamie
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