On Saturday 31 October 2015 06:45 PM, Noam Camus wrote:
> From: Noam Camus <[email protected]>
>
> Add internal tick generator which is shared by all cores.
> Each cluster of cores view it through dedicated address.
> This is used for SMP system where all CPUs synced by same
> clock source.
>
> Signed-off-by: Noam Camus <[email protected]>
> Cc: Daniel Lezcano <[email protected]>
> Cc: Rob Herring <[email protected]>
> ---
[snip]
> +/*
> + * To get the value from the Global Timer Counter register proceed as
> follows:
> + * 1. Read the upper 32-bit timer counter register
> + * 2. Read the lower 32-bit timer counter register
> + * 3. Read the upper 32-bit timer counter register again. If the value is
> + * different to the 32-bit upper value read previously, go back to step 2.
> + * Otherwise the 64-bit timer counter value is correct.
> + */
> +static cycle_t nps_clksrc_read(struct clocksource *clksrc)
> +{
> + u64 counter;
> + u32 lower;
> + u32 upper, old_upper;
> + int cpu;
> + int cluster;
> + void *lower_p, *upper_p;
> + unsigned long flags;
> +
> + local_irq_save(flags);
> + cpu = smp_processor_id();
> + cluster = cpu >> NPS_CLUSTER_OFFSET;
> + lower_p = (void *)nps_msu_reg_low_addr[cluster];
> + upper_p = lower_p + 4;
> + local_irq_restore(flags);
> +
> + upper = ioread32be(upper_p);
Consider using the _relaxed macros even if your platform doesn't have specific
IO
barriers.
> + do {
> + old_upper = upper;
> + lower = ioread32be(lower_p);
> + upper = ioread32be(upper_p);
> + } while (upper != old_upper);
> +
> + counter = upper;
> + counter <<= 32;
> + counter |= lower;
It is easier to read:
counter = (upper << 32) | lower;
> + return (cycle_t)counter;
> +}
> +
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