Noam,
On Sat, 7 Nov 2015, Noam Camus wrote:
> >From: Thomas Gleixner <[email protected]>
> >> + write_aux_reg(AUX_IENABLE, ienb);
>
> >I can see how that works for per cpu interrupts, but what happens if
> >two cpus run that concurrent for two different interrupts?
>
> Each CPU got its own HW copy of auxiliary register IENABLE, so
> concurrent access won't be a trouble.
Please put a comment into the code explaining it.
Thanks,
tglx
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