On Wed, Nov 11, 2015 at 12:03:39PM +0530, Bharat Kumar Gogada wrote: > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > > Signed-off-by: Bharat Kumar Gogada <[email protected]> > Signed-off-by: Ravi Kiran Gummaluri <[email protected]>
I acked v7. Please add acks when sending a new version. Acked-by: Rob Herring <[email protected]> -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
