On Tue, Jan 05, 2015 at 04:58AM, Han Xu wrote:
> On Thu, Dec 24, 2015 at 07:00:18PM +0800, Yuan Yao wrote:
> > Add R/W functions for big- or little-endian registers:
> > The qSPI controller's endian is independent of the CPU core's endian.
> > So far, the qSPI have two versions for big-endian and little-endian.
> >
> > Signed-off-by: Yuan Yao <yao.y...@nxp.com>
> > ---
> > Changed in v3:
> > Update my email to <yao.y...@nxp.com>
> >
> > Changed in v2:
> > Rebase to the lastest code.
> > ---
> > drivers/mtd/spi-nor/fsl-quadspi.c | 157
> > +++++++++++++++++++++++---------------
> > 1 file changed, 97 insertions(+), 60 deletions(-)
> >
> > diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c
> > b/drivers/mtd/spi-nor/fsl-quadspi.c
> > index 54640f1..04e8a93 100644
> > --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> > +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> > @@ -275,6 +275,7 @@ struct fsl_qspi {
> > u32 clk_rate;
> > unsigned int chip_base_addr; /* We may support two chips. */
> > bool has_second_chip;
> > + bool big_endian;
> > struct mutex lock;
> > struct pm_qos_request pm_qos_req;
> > };
> > @@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode(struct
> > fsl_qspi *q)
> > }
> >
> >
> > @@ -954,6 +990,7 @@ static int fsl_qspi_probe(struct platform_device *pdev)
> > if (IS_ERR(q->iobase))
> > return PTR_ERR(q->iobase);
> >
> > + q->big_endian = of_property_read_bool(np, "big-endian");
> once again, please document the new property.
Thanks for your review.
I have already send the patch named "Documentation: fsl-quadspi: Add optional
properties" to community on Dec 24.
Sorry for forget to send this patch to you.
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