> Hi Bean, > > On Thu, 21 Jan 2016 01:06:48 +0000 > Bean Huo 霍斌斌 (beanhuo) <bean...@micron.com> wrote: > > > Hi, Adam and Boris > > > > For Micron MT25Q ,MT25T and MT35Q, they does not exist this action > > even they are Multi-die devices. So when the last byte of the die > > selected is read, the next byte output is the first byte of next die(not the > same die). > > You can check this by extended address register chapter in our > > datasheet, there are detail Information. > > I never said you were wrong ;), I just asked if it was relevant to > differentiate > the two cases. IOW, would the implementation proposed by Adam work > correctly on all chips? And what is the real performance penalty for > MT25Q ,MT25T and MT35Q if we decide to split the read command in several > reads to handle this cross die case? For this , performance penalty is tiny, can ignore. SPI NOR read performance only depends on SPI I/O clock. Not the same as NAND. > Best Regards, > > Boris > > -- > Boris Brezillon, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com