On Sat, 23 Jan 2016, Antoine Tenart wrote:
> The GPIO base address is read from the GPIOBASE register. The first
> bit must be cleared as it can be hardwired to 1 to represent the i/o
> space. Other bits are either containing the base address of are
> reserved. They should not be cleared as all the chipsets do not have
> the same reserved bits.
>
> Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
> ---
> drivers/mfd/lpc_ich.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
Applied, thanks.
> diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c
> index b514f3cf140d..f13a5ded3958 100644
> --- a/drivers/mfd/lpc_ich.c
> +++ b/drivers/mfd/lpc_ich.c
> @@ -921,7 +921,10 @@ static int lpc_ich_init_gpio(struct pci_dev *dev)
> gpe0_done:
> /* Setup GPIO base register */
> pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
> - base_addr = base_addr_cfg & 0x0000ff80;
> +
> + /* Clear the i/o flag */
> + base_addr = base_addr_cfg & ~BIT(0);
> +
> if (!base_addr) {
> dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
> ret = -ENODEV;
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
